Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-06-12
2002-03-26
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000, C710S110000, C710S116000, C710S119000, C710S240000
Reexamination Certificate
active
06363446
ABSTRACT:
RELATED APPLICATION
The subject matter of this application is related to the subject matter in a co-pending non-provisional application by the same inventor(s) as the instant application and filed on the same day as the instant application entitled, “Apparatus for Selectively Encoding Bus Grant Lines to Reduce I/O Pin Requirements,” having Ser. No. 09/332,279, and filing date Jun. 12, 1999.
BACKGROUND
1. Field of the Invention
The present invention relates to buses in computer systems. More particularly, the present invention relates to a method for selectively encoding bus grant lines to reduce I/O pin requirements.
2. Related Application
Much of the interconnection circuitry in a microprocessor-based computer system is typically aggregated in a “core logic” unit that couples the microprocessor to other parts of the computer system, such as a memory, a peripheral bus and a graphics controller.
Providing such interconnection capability can require a large number of I/O pins to accommodate all of the signal lines. Some computer systems deal with this I/O pin problem by partitioning interconnection circuitry across multiple chips. For example, a typical personal computer system includes a north bridge chip, a south bridge chip, a super I/O chip and an I/O APIC chip to support interconnections between the microprocessor and other components within the computer system. Using multiple chips is expensive because the multiple chips must be integrated together within a circuit board. This leads to additional expense in manufacturing circuit boards and maintaining inventories of each type of chip.
It is preferable to integrate all of the interconnection circuitry in a computer system into a single semiconductor chip. However, the I/O pin limitations on a single chip can present problems. For example, a single core logic chip that includes all of a computer system's interconnection circuitry requires interfaces for a processor bus, a memory bus, an AGP bus for a graphics controller and a PCI bus for peripheral devices. Providing I/O pins for all of these interfaces requires many hundreds of I/O pins, especially if any of the busses support 64 bit transfers. Given present packing technology, this I/O pin requirement can easily exceed the I/O pin limitations of a single semiconductor chip.
Note that many bus signals lines are not utilized as well as they could be. In particular bus grant lines and bus request lines convey very little information. Recall that bus request lines are used by devices on the bus to request control of the bus from a bus arbiter in order to perform bus accesses. Bus grant lines are used by the bus arbiter to grant control of the bus to a requester. In a typical bus, such as the PCI bus, there is one request line and one grant line for each master device on the bus. For example, the PCI bus supports up to seven bus request lines and seven bus grant lines. Note that since the bus arbiter will only grant control of the bus to one device at a time, only one of the bus grant lines will be active at any one time. Hence, bus grant lines typically convey very little information.
In order to conserve on the number of I/O pins used, typical core logic chips provide a limited number of request lines and grant lines. This limits the number of bus master devices that can be supported. Unfortunately, this means that typical core logic chips cannot be used in other computer systems, such as servers, that must support a larger number of bus master devices.
What is needed is a method and an apparatus that allows a number of bus grant lines to be transferred across a smaller number I/O pins.
SUMMARY
One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset. The first subset of request lines is received through a number of input pins from off of the semiconductor chip. During the first mode of operation, the second subset of request lines is received from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. This first mode of operation allows more request lines to be used in conjunction with the plurality of encoded grant lines. During the second mode of operation, the second subset of bus grant lines feeds from the bus arbitration circuit through the bi-directional buffers and I/O pins and off of the semiconductor chip. This second mode of operation allows more pins to be used for grant lines when grant lines are not encoded.
Thus, the present invention facilitates encoding of bus grant lines in a first mode of operation to support additional bus master devices. It also facilitates a second mode of operation in which bus grant lines are not encoded. This second mode reduces cost for systems that do not require additional bus master devices because the second mode does not require external decoding circuitry to decode the bus grant lines.
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patent: 6026046 (2000-02-01), Larson
patent: 6029217 (2000-02-01), Arimilli et al.
patent: 6286068 (2001-09-01), Arimilli et al.
Dharia Rupal
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
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