Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-05
2002-09-03
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S343000
Reexamination Certificate
active
06445052
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metal-oxide semiconductor (MOS) transistor, and more particularly, to a power lateral diffused MOS transistor.
2. Description of the Prior Art
Metal-oxide semiconductor (MOS) transistors are widely used in the semiconductor industry due to their high integration and low consumption of power. When a proper voltage is inputted, MOS transistors can be used as a kind of switch to control the flow of electricity through a device. In high voltage circuits, such as the input and output terminals of electrical equipment, LD MOS transistors are commonly used because of their ability to withstand heavy loads. As development of integrated circuits progresses, control of the manufacturing process of LD MOS transistors becomes an increasingly important issue.
Please refer to
FIG. 1
of the cross-sectional view of the structure of a power LD MOS transistor
11
according to the prior art. The power LD MOS transistor
11
is positioned on the surface of a silicon substrate
12
, having a P-well
22
and an N-well
24
, of a semiconductor wafer
10
. The power LD MOS transistor
11
has a gate layer
38
, positioned on a predetermined area on the surface of the silicon substrate
12
, a field oxide layer
26
, positioned on the surface the silicon substrate
12
and underneath one side of the gate layer
38
. The gate layer
38
has a gate field oxide layer
29
and a gate conductive layer
31
. Two doped areas
34
and
36
are positioned on the surface of the silicon substrate
12
, located adjacent to the gate layer
38
and the field oxide layer
26
, respectively.
Please refer to
FIG. 2
of the top view of the layout of the power LD MOS transistor
11
according to the prior art. In order to prevent accelerated device breakdown caused by the tip effects due to high electrical field, tips in junctions need to be avoided. Thus, the power LD MOS transistor
11
is often structurally designed in the shape of a circle (as shown in
FIG. 2
) or in the shape of a rectangle with two opposing rounded edges, as shown in
FIG. 3
of the top view of the layout of another embodiment of a power LD MOS transistor according to the prior art.
For a function chip or a system on chip (SOC), the operational voltage differs in respect to product requirement. However, raising the bearable value of threshold voltage and current of the power LD MOS according to the prior art can only be accomplished by increasing the channel width through enlargement of the radius or the longitude of the power LD MOS, as shown in FIG.
2
and FIG.
3
. Thus, the integration and the utilization of the area of the wafer are seriously decreased.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a novel structure for the power lateral diffused metal-oxide semiconductor (power LD MOS) transistor with more efficient utilization of the area of a wafer.
In the preferred embodiment of the present invention, a LD MOS transistor is positioned in an active area of a substrate on a semiconductor wafer. The power LD MOS transistor has a source/drain, a first metal layer, a hexagonal-shaped gate, a first plug, a first dielectric layer, a second dielectric layer, a second metal layer, a third dielectric layer and a second plug. The first metal layer is positioned on a second dielectric layer and covers the first dielectric layer, the gate, and the surface of the substrate, and electrically connects with the drain via a first plug. The hexagonal-shaped gate, surrounding the drain, has a first end positioned on the first dielectric layer and a second end connecting with the source. The first dielectric layer is positioned outside the active area of the substrate. The second dielectric layer covers the first dielectric layer, the gate, and the surface of the substrate. The third dielectric layer covers both the second dielectric layer and the first metal layer. The second metal layer is positioned on the third dielectric layer and electrically connects with the drain via a second plug.
It is an advantage of the present invention over the prior art that by positioning multiple power LD MOS transistors in parallel, the channel width can be efficiently increased to raise the bearable values of threshold current and operational voltage without sacrificing integration. The hexagonal-shaped structure of the power LD MOS transistor provided in the present invention is cost-effective since it optimally utilizes the wafer area. As well, the manufacturing process of the present invention is compatible to that of CMOS or SOC and thus the product is much more competitive in the market.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 5440151 (1995-08-01), Crevel et al.
patent: 6133107 (2000-10-01), Menegoli
patent: 2001/0015459 (2001-08-01), Watanabe et al.
patent: 9-51085 (1997-02-01), None
Hsu Winston
Lee Eddie
Wilson Allan R.
LandOfFree
Power lateral diffused MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power lateral diffused MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power lateral diffused MOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2849326