Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
1998-09-16
2002-05-07
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S041000, C712S245000, C712S223000, C712S217000, C711S214000
Reexamination Certificate
active
06385714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus comprising a plurality of work registers, and more particularly to a data processing apparatus which can respond to an instruction for a processing by executing a process using a plurality of work registers.
2. Description of the Related Art
A data processing apparatus having a plurality of work registers called a general-purpose register can understand a variety of instructions. One such instruction can simultaneously designate two or more register operands. For example, a typical operation instruction according to a conventional architecture called RISC can simultaneously designate three registers. The three registers may include, with respect to an add operation instruction, two source registers and one destination register. With such an instruction, two values are retrieved from the two source registers to be added, and the operation result is then stored in the destination register. This method is referred to as a three-register-operand method. A two-register-operand method using an instruction designating two register operands for an operation is also known.
The three-register-operand method requires a fewer number of steps to execute certain operations as compared to the two-register-operand method. That is, when the two-register-operand method is used, one of the source registers is always overwritten by the operation result, which creates a need for one additional step. Specifically, if two or more operation instructions simultaneously designate the same value stored in the same register, that value may need to be first copied to another register before the respective operations are executed. An illustrative example is a case to execute a process in which two values are read from registers rs
1
and rs
2
, respectively, to be used in a binomial operation, and the operation result is stored in a register rd. It is possible to designate the whole process using one instruction according to the three-register-operand method, while it is not possible according to the two-register-operand method. That is, with the two-register-operand method, two instructions are necessary to achieve the above; one for copying a value read from the register rs
1
to the register rd, and the other for executing a binomial operation using the copied value and the value read from the register rs
2
and storing the operating result in the register rd.
The three-register-operand method can effectively reduce the number of instructions, i.e., the number of cycles in which a concerned program is executed. However, an instruction according to this method is lengthy as it includes a larger number of operands than that of the two-register-operand method, which works against the common demand for shorter basic instructions. An example would be a case wherein a data processing apparatus comprising sixteen general-purpose registers employs a 16-bit instruction as a basic instruction. A field of 12 bits is used to designate three register operands, leaving a four-bit field available to contain encoded data regarding the types of an instruction or an operation. This field is, however, not sufficient to do so.
As a method free from the above problem and capable of designating a register operand using an instruction of a shorter length, Japanese Patent Application No. Hei 7-313146 discloses an instruction preparing method and a register designating method.
According to these methods, at least one register designation field consists of a fewer number of bits than other register designation fields. This shorter field is used to hold a register designation code, but not a register number itself used for explicit designation of a register. The register designation code is set corresponding to a register number by a correspondence table. By using m number of bits, 2
m
number of different register codes can be defined. In other words, 2
m
number of registers of all general-purpose registers can be indirectly designated through reference to a corresponding table.
An arrangement in which correspondence between a register designation code and a register number is dynamically changed as a program is being executed has also been proposed but, in general, a correspondence table is used, when a received instruction includes a certain register designation code as an operand, to determine the number of a register designated by the code so that the aimed work register is accessed. Conventionally, a structure for this type of process is achieved by means of, for example, hardware or firmware. Therefore, the register numbers set in the correspondence table are available only for reference, and are not available for use as data when executing a program. This is inconvenient for designers attempt to achieve more precise and flexible control over the data processing apparatus.
In particular, in a case where the content of the correspondence table is changed while a program is being executed, if an interrupt process is received, causing exceptional changes in the operating flow of the ongoing program, the content of the correspondence table which has been built up through the processing of the interrupted program, may be updated during the interrupt processing. Therefore, when the interrupted program is resumed upon completion of the interrupt processing, the correspondence table no longer has the same content as that immediately before the interruption. This may hinder returning to the operating flow.
Also, since all register numbers cannot be designated by register designation codes, selection must be made to determine which work registers are set accessible based on register designation codes. Conventionally, this selection is not always preferable in view of achieving effective processing.
SUMMARY OF THE INVENTION
The present invention has been conceived to overcome the above problems and aims to provide a data processing apparatus which is compatible with the three-register-operand method and which uses instructions reduced in length through employment of a register designation code. Particularly, this apparatus ensures high efficiency in executing a program, and properly resumes a program which was interrupted by other interrupt programs.
According to the present invention, there is provided a data processing apparatus using a stored-program method for executing an operation instructed by an instruction including a register designation code as an operand, comprising: a plurality of work registers identifiable by register numbers each of a typical number of bit length; and a correspondence table for holding at least one of the register numbers as designated register numbers in a state corresponding to register designation codes each of a less than the typical number of bits (standard bit number) and in a readable condition, the correspondence table being referred to by the data processing apparatus when executing the operation.
It may be preferable for the above data processing apparatus to further comprise register number obtaining section for obtaining the designated register number from the correspondence table.
Conventionally, the register numbers, set in the correspondence table and corresponding to register designation codes, are available only for reference so that the data processing apparatus can access a working register based on a register designation code. According to this invention, on the other hand, the register numbers held in the correspondence table can be read in response to, for example, an instruction included in a program, to be used as data.
Further, the above data processing apparatus further comprises designated register number storing section for storing the designated register number read from the correspondence table.
According to the present invention, when the operating flow is changed, such as branching from the main routine processing of the ongoing program to a different process, including a sub-routine or an interrupt or exception handler, the register numbers then held in
Koumura Yasuhito
Matsumoto Kenshi
Miura Hiroki
Pan Daniel H.
Pillsbury & Winthrop LLP
Sanyo Electric Co,. Ltd.
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