Interface between a memory having a given number of address inpu

Details Interface between a memory having a given number of address inpu Interface between a memory having a given number of address inpu

1995-11-21

1998-09-01

Moore, David K.

Electrical computers and digital processing systems: memory

Address formation

711 2, 711 6, 711 1, 711210, 711211, G06F 902, G06F 1202

Patent

active

058026010

ABSTRACT:
An interface between a memory that has "n" address bit inputs and a processor which has "p" address bit outputs (where p<n) and "q" programmable data bit outputs (where q.gtoreq.n-p). The interface includes a logic circuit connected to a byte select bit output, to a memory read-write command bit output and to an appropriately programmed one of the "q" programmable bit outputs of the processor. The logic circuit produces a least significant bit address bit input AI0 defined by the equation AI0=R/W & byte-s OR R/W & I/O0. The interface connects the remaining "p" address bit inputs of the memory succeeding to the "p" address bit outputs of the processor, in order, and connects the remaining "n-p-1" most significant address bit inputs of the memory to the same number of appropriately programmed programmable bit outputs of the processor.

REFERENCES:
patent: 5255382 (1993-10-01), Pawloski
Orlando, R. "EEPROMS ehance microcontroller-based system performance,", EDN Electrical Design News, vol. 35, No. 21, pp. 213-217, Oct. 1990.

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