Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-07
2002-03-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S596000, C438S692000, C438S627000, C438S628000, C438S634000, C438S597000, C438S706000, C438S708000, C438S624000, C438S626000
Reexamination Certificate
active
06358842
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of damascene interconnects using low dielectric constant materials in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
With the continuing reduction in the feature size in the art of semiconductor manufacture, conductive traces and active devices are now fabricated very closely together. This greater proximity has led to the tremendous packing densities of modern ultra large-scale integration (ULSI). With these greater densities and closer device spacings has come the problem of greater capacitive coupling between adjacent circuit elements.
To reduce the capacitive coupling between elements in the circuit, while still achieving the essential electrical isolation, new dielectric materials have been developed and introduced into integrated circuit manufacturing. These new materials typically are based on organic compounds that may also contain inorganic elements, such as silicon. For example, spin-on-glass (SOG) materials, such as silsesquioxane have been introduced. Amorphous carbon dielectric materials and organic polymers have also been applied in place of silicon dioxide. These new materials reduce the dielectric constant of the insulating layer formed, thus improving circuit performance.
There are many difficulties to overcome in using these new materials, however. One problem of particular concern is stripping photoresist. Traditional methods and chemistries used for stripping etching these new materials encounter problems as will be seen in the prior art example.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit device is shown. In this example, a dual damascene via is being formed. A semiconductor substrate
10
is shown. The semiconductor substrate
10
could be composed of silicon or of several microelectronics layers such as insulator layers and conductor layers. Metal traces
14
are formed overlying the semiconductor substrate
10
. A passivation layer
18
overlies and isolates the metal traces
14
. A first low dielectric constant layer
22
is applied overlying the passivation layer
18
. The first low dielectric constant layer
22
comprises either an organic material or a carbon-doped silicon dioxide. An etch stop layer
26
overlies the first low dielectric constant material
22
. A second low dielectric constant material
30
overlies the etch stop layer
26
. The second low dielectric constant layer
30
also comprises either an organic material or a carbon-doped silicon dioxide. A capping layer
34
overlies the second low dielectric constant layer
30
. Finally, a photoresist layer
38
is applied overlying the capping layer
34
.
Referring now to
FIG. 2
, the photoresist layer
38
is patterned to form openings where vias for the dual damascene interconnects are planned. The capping layer
34
, second low dielectric constant layer
30
, etch stop layer
26
, and the first low dielectric constant layer
22
are etched through using the photoresist layer
38
pattern as a mask.
Referring now to
FIG. 3
, the photoresist layer
38
is stripped away. A serious problem in the prior art method is illustrated. The photoresist stripping process can attack the first low dielectric constant layer
22
and the second low dielectric constant layer
30
. A significant amount of the low dielectric constant material can be removed, resulting in the bowing profile
42
shown.
Photoresist is typically stripped by a wet solvent or by an oxygen plasma. Unfortunately, wet solvents can attack interfaces. The oxygen plasma, or ashing, approach is more frequently used to avoid this problem. Oxygen plasmas do not typically damage silicon dioxide dielectric layers. However, the carbon and hydrogen containing low dielectric constant materials are susceptible to attack by the oxygen radicals in the plasma. The bowing damage caused by the oxygen strip is not repairable. It leads to poor damascene copper fill and to via poisoning problems.
Several prior art approaches disclose methods to form interconnecting structures in the fabrication of integrated circuits. U.S. Pat. No. 5,536,681 to Jang et al discloses a process to improve the gap filling capability of O
3
-TEOS. A selective plasma N
2
treatment is performed on a PE-OX layer to reduce the O
3
-TEOS deposition rate and thereby improve the gap fill capability. U.S. Pat. No. 5,759,906 to Lou teaches a method to improve planarization and to eliminate via poisoning in a multiple level metal process. A triple bake sequence is performed on the spin-on-glass (SOG) layer to improve planarization. A high-density plasma fluorinated silicon glass (HDP-FSG) layer is deposited. The HDP-FSG layer is anisotropically etched to form sidewall spacers on the via sidewalls. The presence of the HDP-FSG sidewall spacers eliminates via poisoning. U.S. Pat. No. 5,985,762 to Geffken et al discloses a method to form a copper barrier layer on the sidewalls of vias to prevent via poisoning. The barrier material is bulk deposited and then anisotropically etched to form the sidewall liner. U.S. Pat. No. 5,976,626 to Matsubara et al teaches a method to improve the crack resistance and to eliminate via poisoning. Various thermal treatments are disclosed.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming damascene interconnects in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to form single and dual damascene interconnects where low dielectric constant materials are used.
A yet further object of the present invention is to provide a method to strip photoresist after trench etch such that a sidewall passivation is formed to line the trench.
Another yet another further object of the present invention is to provide a method to form a sidewall passivation that protects the low dielectric constant materials from oxygen plasma damage.
Another yet further object of the present invention is to provide a method to strip photoresist using a sulfur-containing gas that simultaneously forms a sidewall passivation.
In accordance with the objects of this invention, a new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A barrier metal layer is deposited overlying the first passivation layer and the underlying copper conductors and lining the via openings. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
REFERENCES:
patent: 5536681 (1996-07-01), Jang et al.
patent: 5540812 (1996-07-01), Kadomura
patent: 5759906 (1998-06-01), Lou
patent: 5821168 (1998-10-01), Jain
patent: 5976626 (1999-11-01), Matsubara et al.
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6024887 (2000-02-01), Kuo et al.
patent: 6100181 (2000-08-01), You et al.
patent: 6100184 (2000-08-01), Zhao et al.
patent: 6150723 (2000-11-01), Harper et al.
patent: 619
Chooi Simon
Xu Yi
Zhou Mei-Sheng
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Yevsikov V.
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