Memory controller adapted for rapid block access operations

Details Memory controller adapted for rapid block access operations Memory controller adapted for rapid block access operations

1996-04-23

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711154, G06F 1200

Patent

active

058025871

ABSTRACT:
A memory controller has an address counter, a control circuit, and registers for receiving and storing a starting address, a block fetch size value, and write data. The address counter counts from the starting address, thereby generating successive addresses from which data in a memory device are read. When the amount of data designated by the block fetch size value has been read, the control circuit reloads the starting address into the address counter, the address counter generates the same successive addresses again, and the write data are written at these addresses. A block read-and-clear or block read-and-replace operation is thereby carried out. The memory controller may also have registers for storing the read data, and a logic operation circuit for combining the read and write data to carry out a block read-modify-write operation.

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