Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-09-30
2002-04-30
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S153000
Reexamination Certificate
active
06381681
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of computer memory systems, and more particularly to a system and method for shared memory protection in a multiprocessor computer.
BACKGROUND OF THE INVENTION
Multiprocessor computers often include a large number of computer processors that may operate in parallel. One example of parallel processing computer architectures is Cache-Coherent multiprocessors with Non-Uniform Memory Access (NUMA) architecture. Non-Uniform Memory Access (NUMA) architecture is a type of parallel processing architecture in which each processor has its own local memory that can also act as memory for other processors. The parallel processing architecture is referred to as Non-Uniform because memory access times are faster when a processor accesses its own local memory as compared to when a processor borrows memory from another processor.
As the number of parallel processors in a multiprocessor computer increases, the ability to run certain software in parallel across all of the processors diminishes. For example, although scientific software scales well up to a large number of processors, other software such as operating systems run best on a smaller number of processors. Therefore, the processors in a multiprocessor computer are often segmented into cells of processors. Each cell may run separate software such as operating systems. By segmenting processors into cells, one cell may be taken down to perform routine maintenance, to replace boards, to reboot operating systems, or to perform any other task without affecting other cells in the multiprocessor computer. The use of cells gives better reliability since one cell can go down while other cells remain active.
In order to maintain cache coherence and protect memory pages from unauthorized access, a protection scheme is generally used to enable or disable shared access to a memory page in multiprocessor computers. A memory page may consist of memory data and a memory directory that tracks the state of cache lines coupled to the memory page. Conventional memory protection schemes utilize memory protection codes in each memory page with one bit for each processor. The protection code indicates whether a particular processor can access the memory page. As soon as the memory protection bit for a particular processor is disabled, that processor can no longer access the memory page and cannot apply any updates that may be waiting in cache to be applied to the memory page. Therefore the memory page may not have the most current data. Conventional systems have handled this problem by not allowing a cell of processors to be taken down independent of other cells of processors in a multiprocessor computer. Another conventional technique involves complex software to handle problems associated with a memory protection scheme using a single bit to indicate whether a particular processor may access the memory page. Therefore, it is desirable to provide an enhanced shared memory page protection scheme in a multiprocessor computer.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a system and method for shared memory protection in a multiprocessor computer that provides enhanced shared memory protection. In accordance with the present invention, a system and method for shared memory protection in a multiprocessor computer are provided that substantially eliminate and reduce disadvantages and problems associated with conventional shared memory protection schemes.
According to an embodiment of the present invention, a memory protection system for memory shared between multiple processors is provided that includes a multiprocessor computer having a plurality of processor regions and a plurality of memory pages. Each processor region includes one or more processors. Each processor includes a cache, and each memory page includes one or more cache lines for association with the cache of processors within the plurality of processor regions using the memory page. Each memory page includes a set of protection bits associated with each processor region in the plurality of processor regions. The set of protection bits includes an acquire protection bit for each processor region in the plurality of processor regions. The acquire protection bit determining whether the associated processor region is enabled to perform acquire operations on the memory page. The set of protection bits also includes a release protection bit for each processor region in the plurality of processor regions. The release protection bit determining whether the associated processor region is enabled to perform release operations on the memory page.
The present invention provides various technical advantages over conventional shared memory protection schemes. For example, one technical advantage is that separate acquire protection and release protection bits are used for each of several processor regions within the multiprocessor computer. The separate protection bits allow a cell of processors to assure that memory pages are current before terminating all access to the memory pages for a particular processor. Another technical advantage is that memory updates from processors within a cell common to the shared memory page being updated occur immediately without verifying memory protection information. This eliminates the processing overhead associated with memory protection verification when the processor updating the memory page is considered local with respect to that memory page. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.
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Christie Allan James
McCracken David E.
Stuart Fiske James A.
Baker & Botts L.L.P.
Elmore Stephen
Kim Matthew
Silicon Graphics Inc.
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