Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-03
2002-07-09
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06418060
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of programming and erasing non-volatile memory cells, and more particularly, to a method of selectively programming an individual memory cell of a non-volatile memory array.
2. Description of the Prior Art
The market for non-volatile memory has been continuously growing in the past few years, and further growth in the near future is foreseen, especially for flash memories due to their enhanced flexibility compared to electrically programmable read-only memories (EPROMs). There are two major applications for flash memories. One application is the use of non-volatile memory integrated with logic systems to allow software updates, store identification codes, reconfigure systems in the field, or simply to be used in smart cards. The other application is to create storage elements, such as memory boards or solid-state hard disks, made of flash memory arrays that are configured to create storage devices to compete with miniature hard disks.
Typically, a flash memory is programmed by channel hot electrons and erased by Fowler-Nordheim (FN) tunneling. One of the drawbacks of operating flash memory cells by means of the channel hot electron (CHE) is high energy dissipation during programming the flash memory cells. Low operating-voltage ONO type flash memory has been developed to reduce energy dissipation during operation. However, this kind of memory still suffers from high energy dissipation during programming.
FIG. 1
is a cross-sectional view illustrating a conventional oxide-nitride-oxide (ONO) type flash memory cell
10
. As shown in
FIG. 9
, the memory cell
10
includes a P-type well
12
, an N-type source
14
and an N-type drain
16
formed in the P-type well
12
, an ONO structure
20
formed on a surface of the P-type well
12
contacting the N-type source
14
and the N-type drain
16
, and a control gate
18
formed on the ONO structure
20
. The ONO structure
20
comprises, from top to bottom, an insulating layer
22
made of silicon oxide, an isolated charge trapping layer
24
made of silicon nitride, and an insulating layer
26
made of silicon oxide. Since the ONO structure
20
has a large coupling ratio of 1, lower operational voltages are required when programming and erasing the memory cell
10
.
However, there is still a disadvantage of the conventional flash memory composed of the ONO-type memory cell
10
.
FIG. 2
is a cross-sectional schematic diagram illustrating an array
30
of the conventional ONO-type memory cells
10
.
FIG. 2A
is an equivalent circuit of the array
30
of the conventional ONO-type memory cells
10
. As shown in
FIGS. 2 and 2A
, all of the ONO-type memory cells
10
are manufactured on the same P-type well
12
, and a bit line
32
is connected to a diffusion region
34
in the P-type well
12
.
During a programming operation, for inducing the FN tunneling mechanism, a bit line voltage V
BL
is applied to the selected bit line
32
a
, and a word line voltage V
WL
is applied to a selected word line
36
a
so as to program a selected memory cell
10
a
. Since the selected memory cell
10
a
and unselected memory cells
10
b
are all formed on the same P-type well
12
, the applied voltage will also induce the FN tunneling mechanism in the unselected memory cells
10
b
under the selected word line
36
a
. Therefore, the unselected memory cells
10
b
seriously interfere with the operation of the selected memory cell
10
a
, resulting in a loss of programming selectivity and a degradation in the performance of the flash memory. Heretofore, none of the prior art discloses a method of selectively programming an individual memory cell of an ONO non-volatile memory array.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method of programming and erasing non-volatile memory cells to solve the above-mentioned problems.
According to the claimed invention, a method of selectively programming an individual memory cell of a non-volatile memory array includes the following steps. An array of memory cells is provided. Each of the memory cells comprises a well of a first conductivity type. A diffusion drain of the first conductivity type is encompassed by a localized well region of a second conductivity type in the well. A diffusion source of the first conductivity type is laterally formed adjacent to the localized well region in the well. An isolated charge trapping layer is located between the diffusion drain and diffusion source over the localized well region and the well. A gate is located above the isolated charge trapping layer. A first voltage is applied simultaneously to the diffusion drain and the localized well region of a selected the memory cell through a selected bit line. The diffusion source of the selected memory cell is floated. And a second voltage is applied to the gate of the selected memory cell. Thereby, Fowler-Nordheim (FN) tunneling is induced between the isolated charge trapping layer and the localized well region.
It is an advantage of the present invention method that each memory cell of a non-volatile memory array comprises a diffusion drain encompassed by a localized well region, so that interference with neighboring unselected memory cells under a selected word line is effectively prevented during a programming operation using the FN tunneling mechanism. In addition, since the memory cell of the non-volatile memory utilizes an ONO structure as a floating gate, the operational voltages during programming and erasing is substantially reduced. Consequently, the selectivity and the performance of the non-volatile memory are significantly improved. Furthermore, in addition to the FN tunneling mechanism, a hot hole injection and a channel hot electron mechanisms can also be applied to the programming operation of the non-volatile memory array according to the present invention. Since a diffusion drain and the localized well region can share the voltage required in the diffusion drain of the memory cell, the operational voltage is reduced substantially.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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patent: 5661687 (1997-08-01), Randazzo
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patent: 6091635 (2000-07-01), Chi
patent: 6366499 (2002-04-01), Wang
Hsu Ching-Hsiang
Yang Ching-Sung
e-Memory Technology, Inc.
Hsu Winston
Nguyen Tan T.
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