Speculative cache snoop during DMA line update

Details Speculative cache snoop during DMA line update Speculative cache snoop during DMA line update

1996-07-01

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, G06F 1200

Patent

active

058025766

ABSTRACT:
A method and apparatus for facilitating the streaming of data over a system bus between a memory and a DMA device. This is accomplished by doing a speculative cache look-up, or snoop, on a next cache line during or immediately following the access of a current cache line. This is done for DMA transfers when the first DMA address is received, and before subsequent addresses are received. Thus, a determination of whether the cache line is in the cache can be done in advance, allowing the next cache line of data to stream over the bus to or from the cache without waiting for the next address from the system bus or requiring a rearbitration for the system bus.

REFERENCES:
patent: 5511226 (1996-04-01), Zilka
patent: 5577227 (1996-11-01), Finnell et al.
patent: 5659797 (1997-08-01), Zandveld et al.
Jim Handy, "The Cache Memory Book", Academic Press, Inc., ISBN 0-12-322985-5, pp. 60-62, 1993.

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