Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-02-26
1998-09-01
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395500, G06F 1300
Patent
active
058025731
ABSTRACT:
A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representing the detected instructions are then stored in queues, and marked (colored) as not having been executed. After a detected instruction has been executed and completed, the corresponding target in the queue is marked as being completed. During every clock cycle of the apparatus, the verification logic unit monitors the queues for entries (Targets) marked as completed, which are then discarded.
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Lin Zhongru Julia
Malik Nadeem
Saha Avijit
Coulter Kenneth R.
Henkler Richard A.
International Business Machines Corp.
Lall Parshotam S.
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