Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-01
2002-07-02
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000
Reexamination Certificate
active
06414365
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more particularly to a thin-layer silicon-on-insulator (SOD) high-voltage device structure which employs multiple three-dimensional metal-oxide semiconductor (MOS) capacitor structures to achieve multi-dimensional depletion of the drift charge to improve the breakdown-voltage specific “on” resistance figure-of-merit across a wide range of application voltages.
BACKGROUND OF THE INVENTION
There has been various SOI high voltage device structures in which a field plate construction and drift region doping are used to improve the breakdown voltage specific “on” resistance figure-of-merit. Improved “on” resistance for low voltage application has been obtained using trench device structures in bulk silicon technology. Other thin-layer high voltage devices have improved current driving capability.
Recently, multi-dimensional depletion in the drift region has been achieved by inserting shaped PN-junctions into the graded-doped drift region of the device. Thus, the device could support high voltages with higher levels of charge in the drift region, without extensive thermal oxidation process steps. However, there is an alternative structure in which a MOS dielectric can be used to support higher sustainable electric fields. Such a construction can be used to improve the breakdown voltage specific “on” resistance figure-of-merit.
SUMMARY OF THE INVENTION
The present invention contemplates a thin-layer silicon-on-insulator (SOI) high voltage device comprising a semiconductor substrate and a three-dimensional MOS multi-capacitor structure which forms a depletable drift region. The three-dimensional MOS multi-capacitor structure includes a striped geometry of parallel thin, SOI stripes, wherein each SOI stripe is individually circumscribed longitudinally by a respective dielectric layer formed on the semiconductor substrate, and a conducting multi-capacitor field plate layer superimposed on top of the respective dielectric layer and between adjacent dielectric layers circumscribing longitudinally adjacent SOI stripes.
REFERENCES:
patent: 5483482 (1996-01-01), Yamada et al.
patent: 5888854 (1999-03-01), Morihara
patent: 2001/0033024 (2001-10-01), Fraser et al.
Letavic Ted
Simpson Mark
Biren Steven R.
Koninklijke Philips Electronics , N.V.
Wilson Allan R.
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