Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-08-17
2002-09-03
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000, C438S723000, C438S729000, C438S743000
Reexamination Certificate
active
06444586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to removing doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide. More particularly, the present invention is directed to a method of using a high density plasma etcher such that doped silicon dioxide is removed from a structure at a material removal rate that is greater than that of undoped silicon dioxide.
2. The Relevant Technology
Modem integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a semiconductor substrate. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductive substrates described above. The term “doped silicon dioxide” refers to silicon dioxide having a dopant concentration greater than or equal to about 3% by weight. The term “undoped silicon dioxide” is defined as silicon dioxide having a dopant concentration less than about 3% by weight.
The semiconductor industry is attempting to increase the speed at which integrated circuits operate, to increase the density of devices on integrated circuits, and to reduce the price of integrated circuits. To accomplish this task, semiconductor devices, including capacitors, resistors, transistors, diodes, and the like, are continually being increased in number and decreased in dimension in a process known as miniaturization. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate. Efficient packing of these devices requires multilayer topographical design.
One common process for forming a topographical design on a semiconductor substrate involves etching of semiconductor material. The dimensional extent of material removal during an etch process is typically controlled by providing etch-resistant materials in predetermined regions of a semiconductor substrate. An etch-resistant structure that shields underlying material from an etch is known as an etch mask, while etch-resistant material positioned beneath material to be removed is an etch stop. In either case, the etch process is substantially selective to the etch stop or etch mask, while being not selective to the material to be removed.
In one common etching process, an etch-resistant masking layer is deposited and patterned over the semiconductor material to be etched. The pattern formed on the layer of masking material defines a series of openings in the masking material and corresponds to the topographical design to be formed during the etching process. Next, an etchant is applied to the semiconductor material through the pattern openings. A material, which may be doped silicon dioxide, is removed through the pattern openings, while the etch mask protects material positioned directly therebelow. Currently, photoresist material is commonly used as an etch mask. Use of photoresist material in an etch process involves forming, developing, and patterning the photoresist material, applying an etchant to etch the silicon dioxide, and then removing the photoresist material. The multiple steps involved in using photoresist material require time and resources that can increase the cost of producing integrated circuits.
In other applications, an etch-resistant material, such as silicon nitride is commonly used as an etch stop or etch mask material, particularly in connection with etch processes of silicon dioxide with a fluorinated etch chemistry. For example, in a conventional self-aligned etch process for forming a contact opening to an underlying active region on a semiconductor substrate, silicon nitride is usually used on top of a gate stack as an etch stop. The silicon nitride cap prevents overetching and ensures that the resulting contact hole is aligned directly atop the active region.
One of the problems in the prior art with forming a silicon nitride cap is the simultaneous formation of a silicon nitride layer on the back side of a semiconductor wafer. The particular problems depend on the process flow. For instance, where a low pressure chemical vapor deposition is used to deposit silicon nitride, both sides of the semiconductor wafer would receive deposits of silicon nitride. The presence of silicon nitride on the back side of the semiconductor wafer causes stress which deforms the shape of the semiconductor wafer, and can also potentially cause deformation of the crystal structure as well as cause defects in the circuit. Additionally, silicon nitride deposition is inherently a dirty operation having particulate matter in abundance which tends to reduce yield. When a low pressure chemical vapor deposition process is utilized, the silicon nitride layering on the back side of the semiconductor wafer must be removed later in the process flow.
It would be advantageous to have a method for providing an etch mask material that does not require removal after the etching is completed. Further, it would be an advancement in the art to provide an alternative to silicon nitride for use as an etch stop in self-aligned contact formation.
SUMMARY OF THE INVENTION
The present invention relates to etching doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide. According to the invention, a structure is provided having a first region substantially composed of doped silicon dioxide and a second region substantially composed of undoped silicon dioxide. The first and second regions are configured to define a topographical structure to be formed by the selective etch process. A high density plasma system is used to remove doped silicon dioxide from the topographical structure.
A high density plasma system, as defined herein, has two electrodes. The two electrodes are the upper electrode and lower electrode. There is a space or gap between the two electrodes. The upper electrode is sometimes referred to as the upper window. An inductively coupled plasma is usually applied to the upper electrode (or upper window). Sometimes, the power that is applied to the upper electrode can be divided into two parts, such as an outer coil and an inner coil. The power that is applied to the upper electrode is usually referred to, and is referred to herein, as the source power.
A semiconductor substrate of a wafer being etched is situated on the lower electrode where an optional RF power is usually applied thereto. This power is usually referred as to the bias power. The etch under these condition has a plasma density not less than about 10
9
cm
−3
, and the operating pressure is usually at 10 Millitorr (mT) or below.
A high density plasma source with a fluorinated etch chemistry is applied to the structure such that an inductively-coupled power is delivered to the upper electrode in an amount less than about 1000 Watts (W) per 200 mm-diameter wafer surface. Stated otherwise, the source power density can be expressed as an amount less than about 0.032 W/mm
2
or 19.89 W/in
2
. Accordingly, doped silicon dioxide is removed from the structure at a material removal rate that is greater than the rate of removal of undoped silicon dioxide.
In a reactive ion etcher (RIE), only the bottom electrode where the wafer is situated is powered. Thus, the bottom electrode is preferably the same size as the wafer. As such, the power density is defined as the ratio between the power and the wafer surface area. In a high density etcher, however, the source power which generates a plasma in the etcher is applied to the upper electrode or upper window. A coil is situated on the upper window. There is generally no definite shape or
Micro)n Technology, Inc.
Tran Binh X.
Utech Benjamin L.
Workman & Nydegger & Seeley
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