High voltage metal oxide device with enhanced well region

Details High voltage metal oxide device with enhanced well region High voltage metal oxide device with enhanced well region

2001-03-16

2002-09-10

Christianson, Keith (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

With electric field controlling semiconductor layer having a...

Reexamination Certificate

active

06448625

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor MOS devices and more specifically to a high voltage metal oxide device with an enhanced n-well region.
BACKGROUND OF THE INVENTION
When designing high voltage metal oxide (MOS) devices two criteria must be kept in mind. First, the device should have a very high breakdown voltage (V
BD
). Second, the device, when operating, should have as low an on-resistance (RDS
ON
) as possible. One problem is that techniques and structures that tend to maximize V
BD
tend to adversely affect RDS
ON
and vice versa.
To overcome this problem, different designs have been proposed to form devices with acceptable combinations of V
BD
and RDS
ON
. One such family of devices is fabricated according to the reduced surface field (RESURF) principal. These devices utilize an extended drain region (in one embodiment a n-well) to support high off-state voltage (V
BD
). These devices have a maximum number of charges in the drain area of about 1×10
12
cm
−2
before avalanche breakdown occurs. This maximum charge sets up the lowest RDS
ON
possible since RDS
ON
is proportional to the charge in the drain region.
To help alleviate this problem, some devices utilize a top layer of a conductivity type opposite the extended drain region (in one embodiment a p-type layer) inside the drain region. The top layer allows for a drain region having approximately double the charge than previous designs, which decreases the RDS
ON
. The top layer helps to deplete the extended drain when the extended drain is supporting high voltage, thus allowing for high breakdown voltage.
One drawback to this approach is that a high drain concentration under the gate region and adjacent to the channel region can lead to premature breakdown when the device is blocking voltage. Thus, what is needed is a drain region that has a high concentration in most areas but provides for lower concentration under a gate region.


REFERENCES:
patent: 5272098 (1993-12-01), Smayling et al.
patent: 5569937 (1996-10-01), Bhatnagar et al.
patent: 5610432 (1997-03-01), Ludikhuize
patent: 5894156 (1999-04-01), Terashima et al.
patent: 6160290 (2000-12-01), Pendharkar et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6242787 (2001-06-01), Nakayama et al.

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