Mechanism for writing back selected doublewords of cached dirty

Details Mechanism for writing back selected doublewords of cached dirty Mechanism for writing back selected doublewords of cached dirty

1996-11-04

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711117, 711141, 711143, 711144, 711146, 711169, 711210, 36518903, G06F 1200, G06F 1300

Patent

active

058025596

ABSTRACT:
An integrated processor is provided that includes a cache controller which keeps track of a physical address in the system memory which corresponds to each entry within the cache memory. The address tag and state logic circuit further contains state information consisting of a dirty bit allocated for each doubleword (or word) within each line as well as a valid bit for each line. The dirty bit allocated for each doubleword indicates whether that doubleword is dirty or clean, and the valid bit for each line indicates whether the line is valid or invalid. The cache controller further includes a snoop write-back control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master on the local bus. During such a memory cycle of an alternate bus mater, a comparator circuit determines whether a cache hit has occurred. If a cache hit occurs and one or more dirty doublewords are contained within the corresponding line, the snoop write-back control circuit initiates a snoop write-back cycle to write-back only those doublewords within the line that is marked dirty. If two or more doublewords within the hit cache line are marked dirty, the snoop write-back control circuit effectuates the write-back of the dirty data by executing a burst write cycle on the local bus.

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