Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-09-06
2002-07-30
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S329000, C438S421000
Reexamination Certificate
active
06426267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating semiconductor devices, and more particularly to a monolithic high-Q inductance device and a process for fabricating the same.
2. Description of the Prior Art
Many digital and analog circuits have been successfully mass-produced by using VLSI (very large scale integrated) technology. However, radio frequency (RF) circuits, such as those used in cellular telephones, wireless modems, and other types of communication equipment, have not yet been completely implemented with integrated circuits (ICs).
A lump-sum equivalent circuit of a conventional inductance device is shown in
FIG. 1
, in which L indicates the inductance, R
s
the series resistance, and C
d
the parasitic capacitance. Quality factor (hereinafter, Q value) refers to the quality of an inductance device. It is known that the inductance generated by an ideal conducting coil has an infinitely large Q value, and thus there is no energy loss. However, to date, it has not been possible to obtain an inductance device having an infinitely large Q value. Many attempts have been made to decrease the energy loss of the inductance in order to manufacture an inductance device having high Q-value.
A conventional inductance device, as shown in
FIG. 2
, has an inductor formed by a plurality of spiral conducting lines so as to decrease the serial resistance. The numerals in
FIG. 2
indicate elements as follows:
10
~the substrate,
11
~the first dielectric layer,
12
~the conducting layer,
13
~the second dielectric layer,
15
~the via,
16
~the first spiral conducting line,
17
~the third dielectric layer,
20
~the first spiral via,
21
~the second spiral conducting line,
22
~the fourth dielectric layer,
25
~the second spiral via,
26
~the third spiral conducting line, and
27
~the passivation layer. However, in order to have a higher inductance, the spiral conducting line should have a larger number of winding. The wide spiral conducting lines result in a larger surface area and cause large parasitic capacitance, which in turn results in a decreased Q-value.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide an inductance device with high-Q and to provide a method for fabricating the same.
The above objects of the present invention can be achieved by providing a method for fabricating a high-Q inductance device. A first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. A passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device obtained is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. The acid solution can be HF solution, BOE (buffered oxide etchant) solution, buffered HF solution, hot H
3
PO
4
solution, or mixtures thereof.
To decrease the serial resistance further, the inductance device of the present invention can also include at least two spiral conducting lines rather than only one spiral conducting line. The method for fabricating an inductance device having at least two spiral conducting lines includes the steps of:
providing a semiconductor substrate;
forming a first dielectric layer on the semiconductor substrate;
forming a spiral conducting line above the first dielectric layer;
forming a dielectric layer above the spiral conducting line, such that a spiral air gap is formed in the dielectric layer within the space around the spiral conducting line;
forming a spiral via within the dielectric layer above the spiral conducting line;
forming a spiral conducting line on the spiral via;
repeating steps of forming a dielectric layer above the spiral conducting line, forming a spiral via within the dielectric layer above the spiral conducting line, and forming a spiral conducting line on the spiral via for N times, wherein N is an integer equal to or larger than 0;
forming a passivation layer on the last spiral conducting line and the last dielectric layer to obtain an inductance device, such that a spiral air gap is formed in the passivation layer within the space around the last spiral conducting line; and
immersing the inductance device obtained in an acid solution, so as to increase the sizes of the spiral air gaps.
For example, when the inductance device has three spiral conducting lines, the method for fabricating the inductance device includes the following procedures. First, a first dielectric layer is formed on a semiconductor substrate. Then, a first spiral conducting line is formed above the first dielectric layer. Then, a third dielectric layer is formed above the first spiral conducting line and the first dielectric layer, such that a first spiral air gap is formed in the third dielectric layer within the space around the first spiral conducting line. A first spiral via is formed within the third dielectric layer above the first spiral conducting line. Subsequently, a second spiral conducting line is formed on the first spiral via, and a fourth dielectric layer on the second spiral conducting line and the third dielectric layer, such that a second spiral air gap is formed in the fourth dielectric layer within the space around the second spiral conducting line. A second spiral via is formed within the fourth dielectric layer above the second spiral conducting line, and a third spiral conducting line is formed on the second spiral via. A passivation layer is formed on the third spiral conducting line and the fourth dielectric layer, such that a third spiral air gap is formed in the passivation layer within the space around the third spiral conducting line. Finally, the inductance obtained is immersed in an acid solution, so as to increase the sizes of the first, the second, and the third spiral air gaps. The acid solution can be HF solution, BOE solution, buffered HF solution, hot H
3
PO
4
solution, or mixtures thereof.
According to the method for fabricating the high-Q inductance device of the present invention, a spiral air gap is formed in the passivation layer or both in the passivation layer and the dielectric layer within the space around the spiral conducting line. Since air has a very low dielectric constant, the parasitic capacitance can be decreased. Therefore, the Q value of the inductance device of the present invention can be effectively increased. In addition, the size of the spiral air gap is increased by means of immersing the inductance device in an acid solution. Thus, the parasitic capacitance can be further decreased. In addition, by means of the at least one spiral conducting line, the resistance of the inductance device can be decreased.
REFERENCES:
patent: 5095357 (1992-03-01), Andoh et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5641712 (1997-06-01), Grivna et al.
patent: 6303464 (2001-10-01), Gaw et al.
Ladas & Parry
Pham Hoai
Winbond Electronics Corp.
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