Software programmable edge delay for SRAM write enable signals o

Details Software programmable edge delay for SRAM write enable signals o Software programmable edge delay for SRAM write enable signals o

1994-07-08

1998-09-01

Sheikh, Ayaz R.

Electrical computers and digital processing systems: memory

Storage accessing and control

711154, 711155, G06F 1342

Patent

active

058025480

ABSTRACT:
A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) signals in cache-based personal computer systems thereby enabling the system to accommodate a plurality of microprocessor devices.

REFERENCES:
patent: 3753232 (1973-08-01), Sporer
patent: 4453439 (1984-06-01), Koike
patent: 4499536 (1985-02-01), Gemma et al.
patent: 4712190 (1987-12-01), Guglielmi et al.
patent: 5014188 (1991-05-01), Kawamura
patent: 5025366 (1991-06-01), Baror
patent: 5034885 (1991-07-01), Matoba et al.
patent: 5043943 (1991-08-01), Crisp et al.
patent: 5175826 (1992-12-01), Begun et al.
patent: 5201055 (1993-04-01), Izquierdo et al.
Kummer and Webb, Delayed I/O Read/Write Circuit, May 1984, pp. 6364-6365, IBM Technical Disclosure Bulletin, vol. 26 No. 12.

Affiliated with

Also associated with

Rating

Software programmable edge delay for SRAM write enable signals o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Software programmable edge delay for SRAM write enable signals o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Software programmable edge delay for SRAM write enable signals o will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-284423