Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-02-02

2002-09-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S203000, C365S230060

Reexamination Certificate

active

06452833

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-029273, filed Feb. 7, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a dynamic semiconductor memory device for which a measure for improving the retention characteristic of data stored in a memory cell is taken.
In a semiconductor memory device, for example, dynamic random access memory (DRAM), it is required to lower the operation voltage of a memory cell array to keep the reliability high as the size of elements is reduced. If the operation voltage is lowered, the restore potential used for re-writing data into the memory cell is lowered in many cases. Further, if the operation voltage of the memory cell array is lowered, the operation speed of a sense amplifier is lowered which inhibits high-speed operation of the memory device.
If the operation voltage of the memory cell array is lowered, an amount of charges of a signal written into the memory cell is also reduced. Then, a junction leak current flows, and particularly, the retention characteristic of the memory cell which stores “1” data (which is hereinafter referred to as the “1” retention characteristic) is deteriorated. As means for improving the “1” retention characteristic, a Charge Amplifying Boosted Sensing (CABS) Scheme, described in FIG. 1 of an article by K-C Lee et al., entitled “Low Voltage High Speed Circuit Designs for Giga-bit DRAMs,” 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 104-105, is known.
In the CABS Scheme, a pair of dummy capacitors are respectively connected at one end to paired bit lines, and commonly connected at the other ends. At the time of access to the memory cell, the “1” data readout margin is enlarged by raising the potential on the other ends of the paired dummy capacitors.
That is, if the word line potential is raised at the time of access to the memory cell, the signal charge of the cell capacitor in the memory cell is read out to one of the bit lines. As a result, a potential difference occurs between one bit line and the other bit line. Then, the potential of the other ends of a pair of dummy capacitors is changed from the low level to the high level. Thus, the potentials of the pair of bit lines are raised via the pair of dummy capacitors. After this, the potential difference between the paired bit lines is amplified by operating the sense amplifier and data is sensed.
At this time, if it is desired to further raise the potentials of the bit lines by use of the dummy capacitors, it is necessary to increase the capacitance of the dummy capacitor or increase the amplitude of the potential of the other end of the dummy capacitor. However, in order to increase the capacitance of the dummy capacitor, it is necessary to increase the element area of the capacitor, thereby lowering the integration density of the memory cell since the occupying area of the capacitors on the chip becomes larger. Further, since a parasitic capacitor associated with a node of the other end of the dummy capacitor increases, there occurs a problem that the consumption current caused by the charging and discharging operation increases.
Increasing the amplitude of the potential of the other end of the dummy capacitor may be achieved using the potential amplitude between a boosted power supply potential and the ground potential, the potential amplitude between a power supply potential in the chip and a negative potential, or the potential amplitude between a boosted power supply potential and a negative potential instead of the potential amplitude between the power supply potential in the chip and the ground potential. However, since the boosted power supply potential and the negative potential are created by use of a charge pump circuit in the chip, current consumption of the chip increases by an amount consumed in the charge pump circuit.
In the example explained above, an attempt is made to improve the “1” retention characteristic by raising the potentials of both of the paired bit lines using the CABS Scheme. However, in a case where the other ends of the paired dummy capacitors are separated from each other, potentials can be independently supplied thereto and only the potential of the bit line to which data is read out is raised, the same problem as described above occurs.
Further, a coupling capacitor between the bit line and the word line in the memory cell array becomes large depending on the manufacturing process in some cases. In such a case, the bit line potential will be raised owing to the coupling between the bit line and the word line at the “0” data readout time and a problem that the readout margin is lowered occurs in some cases.
In order to cope with the above drawback, a dummy word line technique is provided for enhancing the “0” readout margin by changing a signal on the other end of the dummy capacitor connected to the bit line to which “0” data is read out from the high level to the low level or changing a signal on the other end of the dummy capacitor connected to the bit line which makes a pair with the bit line to which “0” data is read out from the low level to the high level. Like the CABS Scheme, in the dummy word line technique, there occurs a problem that the consumption current-increases due to the charging and discharging currents at the node of the other end of the dummy capacitor when attempting to attain a significant effect or achieve high-speed row access.
In the DRAM field, a DRAM capable of effecting the high-speed readout operation by making row access at high speed is described in, for example, an article by Yasuhara Sato et al., entitled “Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipe-Lined Operation DRAM,” 1998 Symposium on VLSI Circuit Digest of Technical Papers, pp. 22-25, and an article by Shinichiro Shiratake et al., entitled “A Pseudo Multi-Bank DRAM with Categorized Access Sequence,” 1999 Symposium on VLSI Circuit Digest of Technical Papers, pp. 127-130.
If the above CABS Scheme is applied to the DRAMs described in those two documents, there occurs a problem that the current consumed in a CABS Scheme circuit is further increased since the CABS Scheme circuit is always operated when the word line is driven.
Thus, in the conventional semiconductor memory device using the CABS Scheme, there occurs a problem that the consumption current is increased if an attempt is made to attain a significant effect by use of the CABS Scheme.
BRIEF SUMMARY OF THE INVENTION
Accordingly an object of this invention is to provide a semiconductor memory device in which the data retention characteristic of a memory cell can be improved without greatly increasing the consumption current.
According to this invention, there is provided a semiconductor memory device comprising plural pairs of bit lines; a memory cell array having a plurality of memory cells connected to the bit lines of plural pairs; a plurality of first capacitors each having one end and the other end, the one end being connected to one of the bit lines of a corresponding pair among the plural pairs of bit lines and the other end being commonly connected to a first node; a plurality of second capacitors each having one end and the other end, the one end being connected to the other one of the bit lines of a corresponding pair among the plural pairs of bit lines and the other end being commonly connected to a second node; a first driver circuit having an output node connected to the first node, for driving the plurality of first capacitors; a second driver circuit having an output node connected to the second node, for driving the plurality of second capacitors; and an equalizing circuit connected between the first and second nodes, for equalizing potentials of the first and second nodes.
According to this invention, there is provided a semiconductor memory device comprising plural pairs of bit lines; first and second memory cell arrays having a plurality of mem

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