Semiconductor memory device operating at high speed with low...

Details Semiconductor memory device operating at high speed with low... Semiconductor memory device operating at high speed with low...

2001-04-12

2002-05-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S195000, C365S149000

Reexamination Certificate

active

06388934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a large storage capacity semiconductor memory device operating at high speed with low current consumption.
2. Description of the Background Art
Dynamic random access memory (DRAM) is known as one of semiconductor memory devices. In DRAM, information is stored in a capacitor in an electric charge form, the electric charges stored in the capacitor are read out on a corresponding bit line through an access transistor to be amplified by a sense amplifier circuit for data reading.
In such a DRAM, a memory cell consists of one transistor and one capacitor and therefore, an occupation area thereof is small and a large storage capacity memory can be implemented on a small occupation area.
For the purposes of a high speed operation and reduction in current consumption of a semiconductor memory device and for down-sizing of a processing system in recent years, components of the memory device has been miniaturized. With progress in miniaturization of the elements or components, an area of a memory cell capacitor is also reduced and accordingly, a capacitance value thereof is made smaller. With a smaller capacitance of a memory cell capacitor, an amount of held electric charges is decreased when data of the same voltage level is written to the capacitor. In order to compensate for such a reduction in held electric charge amount, a periodical refresh operation is performed. In the refresh operation, data stored in a memory cell capacitor is read out onto a bit line and then, the data is amplified by a sense amplifier to rewrite the amplified data to the original memory cell capacitor.
Therefore, in a smaller element, when a data retention characteristics is degraded, a refresh interval is required to be shorter in order to compensate for such a degradation of the data retention characteristics. When a refresh interval is made shorter, however, an external processor cannot access the DRAM during a refresh operation, resulting in degradation of performance of the processor.
Furthermore, when a refresh interval is shorter, a current consumed in refresh operations increases. Therefore, it is particularly difficult to meet a low standby current condition required in a data holding mode (for example, a sleep mode) of a battery-powered portable equipment or the like. DRAM with a shorter refresh interval could not be applied to an application such as a battery-powered portable equipment or the like requiring a low current consumption.
A pseudo SRAM (PSRAM), which is DRAM operating like an SRAM (static random access memory), has been known as one of a countermeasure for solving such a refreshing problem associated with DRAM. In PSRAM, to in one cycle in memory access, a cycle of performing an ordinary data write/read and a refresh cycle of performing refresh are continuously performed. Since refresh is performed in one access cycle, the refresh can be hidden from external access, whereby DRAM can be apparently operated as SRAM.
In a case of PSRAM, however, two cycles are required in one access cycle and therefore, a problem that a cycle time cannot be made shorter arises. Especially, in a current fabrication technology at the 0.18 &mgr;m level, it is difficult to realize an operating cycle ranging from 70 to 80 nanoseconds (ns), which is required for SRAM.
Configurations for performing refresh independently of external access are disclosed in, for example, Japanese Patent Laying-Open No. 2-21488 (1990), Japanese Patent Laying-Open No. 61-11993 (1986), Japanese Patent Laying-Open No. 55-153194 (1980) and others.
FIG. 50
is a diagram schematically showing a configuration of an array portion of a conventional dynamic type semiconductor memory device. In
FIG. 50
, normal word lines WL and refresh word lines RWL are provided corresponding to respective rows of memory cells MC. In
FIG. 50
, there are representatively shown two normal word lines WL
0
and WL
1
, two refresh word lines RWL
0
and RWL
1
, and two memory cells MC
0
and MC
1
. Normal bit lines BL and /BL and refresh bit lines RBL and /RBL are provided corresponding to the memory cell columns.
The memory cells MC (MC
0
and MC
1
) each include: a data access transistor Tr
1
; a refresh access transistor Tr
2
; and a capacitor C storing information. A main electrode node (storage node) SN of the capacitor C is coupled commonly to the access transistors Tr
1
and Tr
2
. In the memory cell MC
0
, the access transistor Tr
1
couples the storage node SN to the normal bit line BL in response to a signal on the normal word line WL
0
, while the refresh access transistor Tr
2
connects the storage node SN to the refresh bit line RBL in response to a signal on the refresh word line RWL
0
.
In the memory cell MC
1
, the normal access transistor Tr
1
connects the storage node SN to the bit line /BL in response to a signal on the normal word line WL
1
and the refresh access transistor Tr
2
connects the storage node SN to the refresh bit line /RBL in response to a signal on the refresh word line RWL
1
.
A refresh sense amplifier RSA, which is activated in response to a refresh sense amplifier activating signal &phgr;RSE, is provided to the refresh bit lines RBL and /RBL. A sense amplifier SA, which is activated in response to activation of a sense amplifier activating signal &phgr;SE, is connected to the normal bit lines BL and /BL. The normal bit lines BL and /BL are coupled to an internal data line pair IOP through a column select gate CSG responsive to a column select signal Y.
In the configuration shown in
FIG. 50
, in an ordinary data access, the normal word line WL (WL
0
or WL
1
) is driven into a selected state. In this case, data stored in the memory cell MC (MC
0
or MC
1
) is read out onto the bit line BL and /BL. Then, the data read out onto the normal bit line BL and /BL is differentially amplified by the (normal) sense amplifier SA. Thereafter, the column select gate CSG is made conductive by the column select signal Y to couple the normal bit lines BL and /BL to the internal data line pair IOP and data write/read is performed.
The refresh word line RWL (RWL
0
or RWL
1
) is driven into a selected state asynchronously with the data access operation. Responsively, a storage data of the memory cell MC (MC
0
or MC
1
) is read out onto the refresh bit lines RBL and /RBL and the memory cell data is differentially amplified and latched by the refresh sense amplifier RSA to then rewrite the data to the original memory cell.
Accordingly, a refresh operation can be internally performed asynchronously with a data access operation and therefore, the refresh operation in the semiconductor memory device can be hidden from an outside, whereby the semiconductor memory device can be accessed independently of an internal refresh cycle.
As shown in
FIG. 50
, data access and refresh can be performed asynchronously with each other by separately providing the normal bit line pair BL and /BL for performing data access and the refresh bit line pair RBL and /RBL for performing refresh.
However, when refresh and data access are simultaneously in performed on the same memory cell prior to a sense operation, a problem as described below occurs. That is, for example, when the normal word line WL
0
and the refresh word line RWL
0
are simultaneously driven into a selected state, the capacitor C of the memory cell MC
0
is connected to the bit lines BL and RBL through the access transistors Tr
1
and Tr
2
. The bit lines BL and RBL have substantially the same parasitic capacitance with each other. Hence, electric charges stored in the capacitor C are transmitted to the bit lines BL and RBL so as to be distributed thereon. That is, a change in voltage on the bit line is reduced to be, in this case, ½ times as large. The sense amplifier SA amplifies a voltage difference (readout voltage) &Dgr;V between the bit lines BL and /BL as shown in FIG.
51
. Hence, when the capacitor C is connected to the bit lines BL and RBL b

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