Electrically selectable and alterable memory cells

Details Electrically selectable and alterable memory cells Electrically selectable and alterable memory cells

1997-06-30

2002-07-16

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000

Reexamination Certificate

active

06420753

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to electrically programmable non-volatile memory cells and arrays, and, more particularly, to electrically erasable programmable non-volatile memory cells and arrays where memory cells in a memory array can be selectively altered on a byte-block basis.
BACKGROUND OF THE INVENTION
There are several types of memory cell structures in the field of non-volatile memory.
One type of non-volatile memory uses a storage transistor having a so-called floating gate. The floating gate is generally fabricated between the control gate and the substrate and is not directly connected to any terminals or any specific structures. If the floating gate is neutral (no or minimal charges stored), it does not affect the electric field generated by the control gate that affects the channel region between the source and drain terminals. In effect, the storage transistor operates like a normal MOS transistor. If the floating gate is charged (storing electrons), the electrons in the floating gate react to the electric field generated by the control gate and generate an electric field in the channel region that is opposite in polarity to the electric field generated by the control gate. From this technology, a class of non-volatile memory devices known as electrically erasable programmable read only memory or EEPROM has been developed.
Referring to
FIG. 1
a
, one type of EEPROM storage transistor cell structure is the FLOTOX (Floating Gate Tunnel Oxide) cell structure. Here, there is a polysilicon control gate
10
where a control voltage V
CG
may be applied, a polysilicon floating gate
12
, a source terminal having a source voltage potential V
S
, a drain terminal having a drain voltage potential V
D
, and another polysilicon
14
over two n-type regions,
16
and
18
, forming a select transistor. An inter-poly dielectric region
26
is defined between the two polysilicon pieces
10
and
12
(control gate and floating gate); two gate-dielectric regions
28
and
32
are defined by the respective polysilicon areas; and a tunnel dielectric region is defined by the tunnel window region
22
of the polysilicon piece
12
(floating gate). Due to the unique shape of the control gate
10
and the floating gate
12
, a tunnel window region
22
is defined to allow the tunneling of electrons. This cell structure may be schematically represented as in
FIG. 1
b
where a FLOTOX transistor
36
is coupled with a select transistor
38
. In operation, the select transistor
38
has to be turned on in order to operate the FLOTOX transistor
36
.
Programming of the FLOTOX memory cell is carried out by applying a relatively high voltage pulse between the control gate
10
and the drain terminal
18
when there is a positive voltage applied at the select gate terminal
14
. The high voltage pulse initiates carrier generation in the substrate and causes electrons to penetrate the tunnel-dielectric region
30
and accumulate in the floating gate
12
. In a likewise manner, in erasing the memory cell, an inverse voltage is applied between the gate and drain terminals. Thus, the negative electrons in the floating gate are drawn to the drain through the thin tunnel oxide.
The erase and program operations are achieved by taking advantage of the Fowler-Nordheim tunneling mechanism occurring between the floating gate
12
and the silicon substrate
24
through a thin oxide called the tunnel oxide
30
. A tunnel window
22
defines the area of the tunnel oxide where a large tunnel window would improve the speed of the erase/program operation but would also increase the cell size as well. A thinner tunnel oxide region
30
would reduce the tunneling voltage requirement and reduce the erase/program operation time. However, such a memory cell is more difficult to manufacture and may have greater reliability problems.
There are several problems with the FLOTOX memory cell. The memory cell requires a conductive n-type region on the p-type substrate
24
directly in the tunnel window area
22
. Since this n-type region can not be fabricated by the self-alignment method, it requires an additional processing step which translates to higher processing cost and lower yield. Additionally, an electric field of about 10 mega volt per centimeter is required for tunneling to occur through the oxide, which translates to a voltage potential difference between the control gate and the drain terminal in the range from 16 volts to 20 volts. This is a relatively high voltage requiring special drain and source formation (at the drain
18
and source
34
terminals for the select transistor and at the drain terminal
34
for the FLOTOX transistor). These high voltage junctions would in turn require the select transistor to have a longer channel or have an overall larger area. The traditional FLOTOX erase and program operation time are typically in the range of 1 ms to 3 ms each with approximately 18 to 20 volts applied. The total write time for this type of memory cell is 10 ms maximum.
Referring to
FIG. 2
a
, another important type of non-volatile memory is the flash memory. In a flash memory cell, there is a drain (
40
or
42
) and source (
40
or
42
) region deposited on and within a substrate
44
. An insulating layer is deposited over the substrate and the drain and source regions,
50
and
52
. Over the insulating layer, a floating gate
48
is disposed in such a manner to partially overlap one of the regions. A second insulating layer is then deposited over the floating gate
48
. A control gate
46
is then disposed over the floating gate
48
and partially overlapping the other region.
In operation, the flash memory cell is erased when the drain and source terminals are connected to ground and a high voltage is applied at the control gate
46
, causing electrons in the floating gate
48
to tunnel to the control gate
46
. Comparing the tunneling process occurring in the FLOTOX memory cell, the tunneling of electrons here is a faster process requiring lower voltages potential across the respective terminals. Additionally, the typical erase time for the flash memory cell is less than 1 ms with approximately 14 volts applied. The erase time and/or (lower) voltage potential can be further improved by modifying and optimizing the dimensions of the memory cell.
To program the memory cell, the control gate
46
is set to be barely-on (around 2 volts), the terminal connected to region
40
, away from the floating gate
46
, is connected to ground, and the terminal connected to regions
42
closer to the floating gate
46
is provided with a high voltage, generally around 12 volts. In this manner, an electric field is generated in the direction of region
40
away from the floating gate, causing electrons to travel through the channel region and be injected into the floating gate
48
, thereby charging the gate and programming the memory cell. The flow of the electrons in this process called hot carrier injection is as illustrated by the arrows. The programming operation by hot electron injection provides a much faster programming time when compared with the programming time of traditional FLOTOX programming operations. The typical programming time for a flash memory cell is in the range of lus (micro-second) to 100 us depending on the process, the device size, and the voltage potential applied, while the typical programming time for the FLOTOX memory cell is around 3 ms. The flash memory cell is a much faster device where time for writing data into the memory cell (T
write
) equals the time to erase the data in the memory cell (T
erase
) which is about 1 ms plus time to program the memory cell (T
prog
) which is about 100 us. This time is faster than the write time for the FLOTOX memory cell. Moreover, a major advantage of the flash memory is that from a processing point of view, the flash memory cell requires fewer and less difficult processing steps since the self-alignment method can be used. The schematic representation of the
FIG. 2
a
is illustrated in
FIG. 2
b
which is the

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