Gate input protection with a reduced number of antenna diodes

Details Gate input protection with a reduced number of antenna diodes Gate input protection with a reduced number of antenna diodes

1999-07-22

2002-05-14

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06389584

ABSTRACT:

FIELD OF THE INVENTION
This application relates to integrated circuit (IC) design automation and, more specifically, to gate input protection design.
A conventional approach to designing an IC consists of assembling the IC using standard of-the-shelf IC elements known as cells. Cells are also referred to as logic gates or gates. Automated IC design makes use of a library, table or database of cells (hereafter collectively referred to as the “cell library”). The structure of IC elements, including MOS devices, is determined by the contents of cells suitably selected from the cell library. Devices such as NMOS (n-type MOS), PMOS (P-type MOS), MOSFET (MOS field effect transistor), CMOS (complimentary MOS), etc., are collectively referred to herein as the MOS devices. Moreover, ICs that include MOS devices are known as MOS ICs or, simply, ICs (hereafter, ICs).
To illustrate the structure of MOS devices in ICs,
FIGS. 1
a
and
1
b
, show a somewhat simplified cross section of an IC
1
with a MOS transistor
10
or
20
. The MOS transistor
10
in
FIG. 1
a
is a p-channel transistor. The MOS transistor
20
in
FIG. 1
b
is an n-channel transistor. The MOS transistors
10
and
20
are shown as being produced in lightly doped p-type and n-type silicon substrates
12
and
22
, respectively. A typical MOS transistor includes source, drain and channel regions, as well as a gate separated from these regions by a thin layer of (dielectric) insulation.
Hence, as is further shown, for each of the MOS transistors
10
and
20
, two heavily doped n-type and p-type regions, respectively, are created in the substrate
12
and
22
. The heavily doped regions in the MOS transistor
10
are indicated as n+ source
14
a
and n+ drain
14
b
. The heavily doped regions in the MOS transistor
20
are indicated as p+ source
24
a
and p+ drain
24
b.
In MOS transistor
10
, the channel
2
in the n-type substrate
12
between the source
14
a
and drain
14
b
is a region of p-type material. In MOS transistor
20
, the channel
4
in the p-type substrate
22
between the source
24
a
and drain
24
b
is a region of n-type material. Through the channel
2
(and
4
), a current of the majority of charge carriers flows from the source
14
a
(and
24
a
) to the drain
14
b
(and
24
b
).
In order to insulate the gate
16
, as previously described, the gate
16
(and
26
) is overlaid on a thin layer of insulating material
18
(and
28
) that rests over the surface of the structure. The insulating material has dielectric properties. The thin layer of insulation is grown, for example, as a layer of silicon dioxide (SiO
2
), and the gate area is formed from a metal such as polysilicon. The gate covers substantially the entire channel region.
Furthermore, holes or vias (not shown) are cut or etched into the thin layer of insulation to make room for metal contacts. The metal contacts, designated as S, G and D, provide electrical connections to the source
14
a
and
24
a
, drain
14
b
and
24
b
and gate
16
and
26
, respectively.
As a result of their physical structure, MOS transistors exhibit certain inherent characteristics including a gate capacitance. More specifically, the metal area of the gate
16
and
26
, in conjunction with the dielectric thin layer of insulation
18
and
28
and the channel, form a parallel plate capacitor. This capacitor is known as the gate capacitor. The insulation layer under the gate area
16
(and
26
) is referred to as the gate oxide layer or, simply, gate oxide.
To illustrate the structure of a plurality of MOS devices in an IC,
FIGS. 1
c
and
1
d
show a somewhat simplified cross section of ICs
100
and
200
with a plurality of MOS transistors
110
,
120
,
210
and
220
, respectively. Each of the MOS transistors
110
,
120
,
210
and
220
is structured in a manner as explained above. In
FIG. 1
c
, the MOS transistors
110
and
120
are constructed in a p-type substrate, where the p+ regions of the source
114
a
and drain
114
b
in MOS transistor
110
are diffused into an n-type well
118
. Conversely, in
FIG. 1
d
, the MOS transistors
210
and
220
are constructed in an n-type substrate, where the n+ regions of the source
224
a
and drain
224
b
in MOS transistor
210
are diffused into a p-type well
218
.
Regions of insulation shown as the silicon dioxide (SiO
2
) regions
128
(and
228
) separate between adjacent MOS transistors. For example, insulation region
128
b
(and
228
b
) separates between adjacent MOS transistors
110
and
120
(and
210
and
220
) in IC
100
(and
200
). Moreover, for each MOS transistor, the metal area of the respective gates
116
and
126
(and
216
and
226
), in conjunction with the dielectric thin layer of insulation
130
(and
230
) and the channel (not shown), forms a parallel plate capacitor. For each MOS transistor, this capacitor is its gate capacitor, and the insulation layer
130
(and
230
) under the gate area is its gate oxide layer or, simply, the gate oxide.
After assembling the thousands of unconnected cells for creating the IC, the interconnection of the cells can be achieved by a metallization process. Metallization includes the creation of a metal layer for interconnecting between the cells. A metal layer is made out of a conductive material (e.g., metal) according to a pattern specified to implement the particular IC function. In automated IC design, the metal layer pattern is created by routing that implements the specified IC function. The metal layer is processed according to the routed pattern. For example, in the production of CMOS devices, plasma etching techniques are used to produce the pattern on the metal layer.
Metal layers are individually created and then connections are made between them as needed. This allows interconnections defined by pattern of the various metal layers to carry signals to and from cells in similar or different levels.
FIGS. 2
a
and
2
b
show a somewhat simplified diagram of an IC
300
with a plurality of partially connected MOS transistors
302
and
304
.
Interconnects in one metal layer (M
2
)
342
and
344
may be connected to several gate inputs
316
and
326
of MOS transistors
302
and
304
before connections between this (M
2
) and other metal layers (M
3
)
340
can be completed. Until the connections are completed, such gates remain open circuited and the interconnects that are attached to them behave as antennas. The antenna-behaving interconnects receive static charge from the surrounding environment when, for example, a next higher metal layer (M
3
)
340
is plasma-etched. It may be recalled that each gate is associated with a gate capacitor (not shown). For that reason, the static charge
350
is induced by the antenna-behaving interconnects at the respective gate inputs
316
and
326
as a collection of charges at their gate capacitors.
Charges
350
that accumulate in a gate capacitor can cause a gate-to-source voltage (V
GS
)
360
and
370
to exceed a breakdown voltage. An accumulation of charges on an open-circuited gate may result in a large enough field to punch through the dielectric gate oxide. Since a gate oxide is extremely thin, it may easily be damaged by the excessive voltage. This effect is magnified as the length of interconnects increases.
As the density of MOS devices in IC increases, the structure of MOS devices gets smaller and, in turn, their respective gate oxide layers become even thinner. Moreover, to achieve higher performance and reduce power consumption, MOS devices, particularly CMOS devices, have been operating under lower supply voltage conditions and with smaller gate sizes. Hence the accumulation of charges due to the antenna behavior of the interconnects becomes more critical.
To prevent the accumulation of static charge in the gate capacitor of MOS devices, gate protection is usually included at the gate input of the MOS devices. The protection mechanism invariably makes use of clamping or antenna diodes (hereafter collectively referred to as antenna diodes)

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