Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-11-22
2002-07-09
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
Reexamination Certificate
active
06417081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a multi-bit flash electrically erasable programmable read only memory (EEPROM) cell with a bitline.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride oxide (ONO) layer of the device. Other examples of ONO EEPROM devices are disclosed in U.S. Pat. Nos. 5,635,415; 5,768,192 and PCT patent application publication WO 99/07000, the contents of each reference are hereby incorporated herein by reference.
In the case of known NROM devices, such as schematically shown in
FIG. 1
, an NROM cell
100
included a grid of polygates or word lines
102
and buried bitlines
104
. The bitlines
104
were formed in the N+region of the substrate so that a higher density of bitlines can be formed that region versus when the bitlines were formed in a metal layer. As shown in
FIG. 2
, the junction formed between the buried bitlines
104
and the substrate had a severe differential change going from the bitline region to the substrate region which caused the capacitance of the junction to be large. It is well known that the higher the capacitance of the junction, the more the read speed is slowed down. Select transistors
106
were required to compensate for the high capacitance and the slowing of the read speed. The overall size of the flash memory cell array increases the more select transistors
106
that are employed in the array.
SUMMARY OF THE INVENTION
One aspect of the invention regards a process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.
The above aspect of the present invention provides the advantage of decreasing the junction capacitance and decreasing the number of select transistors needed in a memory cell array.
The above aspect of the present invention provides the advantage of reducing the total size of a memory array.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
REFERENCES:
patent: 5084418 (1992-01-01), Esquivel et al.
patent: 5635415 (1997-06-01), Hong
patent: 6137728 (2000-10-01), Peng et al.
Streetman, B.G.; “Solid State Electronic Devices,” 1980, Prentice Hall, Second edition, pp. 204-206.
Amin & Turocy LLP
Christianson Keith
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