Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-10-09
2002-01-29
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S167000, C710S005000, C365S194000
Reexamination Certificate
active
06343352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the transfer of data in digital systems. More specifically, the present invention relates to a protocol and apparatus that provide improved interconnect utilization. In particular, a two-step write operation according to the present invention avoids resource conflicts, thus permitting read and write operations to be issued in any order while maintaining continuous data traffic.
2. Description of the Related Art
A computer, such as a computer system
10
shown in
FIG. 1A
, typically includes a bus
12
which interconnects the system's major subsystems such as a central processing unit (CPU)
14
, a main memory
16
(e.g., DRAM), an input/output (I/O) adapter
18
, an external device such as a display screen
24
via a display adapter
26
, a keyboard
32
and a mouse
34
via an I/O adapter
18
, a SCSI host adapter
36
, and a floppy disk drive
38
operative to receive a floppy disk
40
. SCSI host adapter
36
may act as a storage interface to a fixed disk drive
42
or a CD-ROM player
44
operative to receive a CD-ROM
46
. Fixed disk
42
may be a part of computer system
10
or may be separate and accessed through other interface systems. A network interface
48
may provide a connection to a LAN (e.g., a TCP/IP-based local area network (LAN)) or to the Internet itself. Many other devices or subsystems (not shown) may be connected in a similar manner. Also, it is not necessary for all of the devices shown in
FIG. 1A
to be present to practice the present invention, as discussed below. The configuration of the devices and subsystems shown in
FIG. 1A
may vary substantially from one computer to the next.
In today's high-performance computers, the link between the CPU and its associated main memory (e.g., CPU
14
and main memory
16
, respectively) is critical. Computer programs currently available place imposing demands on a computer's throughput capabilities. This need for increasingly higher bandwidth will continue.
One method for improving the throughput of this interface is to provide a dedicated bus between CPU
14
and main memory
16
. Such a bus is shown in
FIG. 1A
as a memory bus
50
. Memory bus
50
allows CPU
14
to communicate data and control signals directly to and from main memory
16
. This improves computational performance by providing a pathway directly to the system's main memory that is not subject to traffic generated by the other subsystems in computer system
10
. In such systems, the pathway between main memory
16
and bus
12
may be by way of a direct memory access (DMA) hardware construct for example.
FIG. 1B
illustrates a block diagram in which components (e.g., CPU
14
and main memory
16
) communicate over an interconnect
60
in order to process data. Interconnect
60
is a generalization of memory bus
50
, and allows one or more master units such as master units
70
(
1
)-(N) and one or more slave units, such as slave units
80
(
1
)-(N). (The term “N” is used as a general variable, its use should not imply that the number of master units is identical to the number of slave units.) Components attached to interconnect
60
may contain master and slave memory elements. In the case where interconnect
60
serves as memory bus
50
, CPU
14
communicates with main memory
16
over interconnect
60
using pipelined memory operations. These pipelined memory operations allow maximum utilization of interconnect
60
, which is accomplished by sending data over interconnect
60
as continuously as is reasonably possible given the throughput capabilities of main memory
16
.
The block diagram of
FIG. 1B
is applicable to intrachip, as well as interchip, communications. It will be understood that one or more of slave units
80
(
1
)-(N) may consist of other components in addition to memory (e.g., a processor of some sort). The block diagram of
FIG. 1B
can, of course, be simplified to the case of a system having only a single master.
FIG. 1C
shows a memory device
100
. Memory device
100
might be used in a computer system, for example, as main memory
16
of computer system
10
, or in combination with similar devices to form main memory
16
. Memory device
100
is capable of being read from and written to by a memory controller (not shown). An interconnect
110
is used to communicate control information over control lines
112
and data over data lines
114
from the memory controller to memory device
100
. Interconnect
110
is thus analogous to memory bus
50
. To support such communications and the storage of data, memory device
100
typically includes three major functional blocks.
The first of these, a transport block
120
, is coupled to interconnect
110
. Interconnect
110
, which includes control signal lines
112
and data signal lines
114
, is used to read from and write to memory device
100
. Interconnect
110
provides the proper control signals and data when data is to be written to memory device
100
. Transport block
120
receives these signals and takes the actions necessary to transfer this information to the remaining portions of memory device
100
. When memory device
100
is read, transport block
120
transmits data as data signal lines
114
in response to control signal lines
112
. Transport block
120
includes a control transport unit
122
which receives control signal lines
112
, and controls a read data transport unit
124
and a write data transport unit
126
to support the communication protocol used in transferring information over interconnect
110
(e.g., transferring information between CPU
14
and main memory
16
over memory bus
50
).
In its simplest form, transport block
120
is merely wiring, without any active components whatsoever. In that case, control transport unit
122
would simply be wires, as read data transport unit
124
and write data transport unit
126
would require no control. In effect, transport block
120
is not implemented in such a case. Another possible configuration employs amplifiers to provide the functionality required of transport block
120
. In yet another possible configuration, transport block
120
includes serial-to-parallel converters. In this case, control transport unit
122
controls the conversion performed by read data transport unit
124
and write data transport unit
126
(which would be the serial-to-parallel converters). Other equivalent circuits may also be used with equal success.
The second of the major functional blocks is an operations block
130
. Operations block
130
receives control information from transport block
120
, more specifically from control transport unit
122
, which provides the requisite signals to a control operation unit
150
.
In
FIG. 1C
, control operation unit
150
is implemented as an architecture designed to control generic DRAM memory cells. A specific DRAM memory cell architecture (or other architecture), however, may require different control signals, some or all of which may not be provided in the architecture shown in FIG.
1
C. Control operation unit
150
includes a sense operation unit
132
, a precharge operation unit
134
, and a core transfer operation unit
136
.
Data being read is transferred from the third functional block, a memory core
180
, via data I/O bus
185
to a read data operation unit
160
. From read data operation unit
160
, the data being read is transferred to read data transport unit
124
(and subsequently, onto data signal lines
114
) in response to control signals from control operation unit
150
. Read data operation unit
160
may consist of, for example, data buffers (not shown) that buffer the outgoing data signals to drive read data transport unit
124
.
Data to be written is transferred from write data transport unit
126
to a write operation unit
170
in response to control signals from control transport unit
122
(if used) and control operation unit
150
. Write data operation unit
170
receives write data from write transport unit
126
, which is pass
Davis Paul G.
Hampel Craig E.
Ware Frederick A.
Bataille Pierre-Michel
Kim Matthew
Rambus Inc.
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