Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-05
2002-01-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S333000
Reexamination Certificate
active
06339242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a nonvolatile memory in which a plurality of transistor elements are arranged, and to a method of fabricating such a device.
2. Description of the Related Art
Semiconductor devices of various configurations are currently in practical use, and in nonvolatile memory such as flash memory, EPROM, and EEPROM, transistor elements having floating gates (hereinbelow abbreviated as “FG”) are arranged in a two-dimensional form as memory cells. In this case, the FG of the transistor elements hold injected electrons, by which nonvolatile storage of binary data or multivalue data is realized.
This type of nonvolatile memory also has various modes, with the FN (Fowler-Nordheim) tunneling mode and CHE (Channel Hot Electron) mode as modes of writing/erasing. When erasing stored data in the AND flash memory of the FN tunneling mode, for example, electrons are drawn out from the FG of transistor elements, which are the memory cells; a voltage of −20 (V) is therefore applied to the control gate (hereinbelow abbreviated as “CG”) that confronts the FG, with the substrate as 0 (V). Thus, making the confronting areas of FG and CG greater than the confronting areas of the FG and channel and increasing the capacitance enables a reduction of the voltage that must be applied to CG to inject prescribed electrons to the FG.
A semiconductor device in which the confronting areas of the FG and CG of transistor elements are increased is disclosed in “A 0.24-um
2
Cell Process with 0.18-um Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memories” (IEEE Tech. Dig. IEDM (1997) pp. 275).
Referring now to
FIGS. 1
a
and
1
b,
a simple explanation is next presented regarding the semiconductor device described in the above publication.
FIG. 1
a
is a vertical sectional view in which the semiconductor device is cut at the position of a transistor element, and
FIG. 1
b
is a vertical section in which a semiconductor device is cut at a position between transistor elements.
In the interest of simplifying the explanation, the vertical (up-down) and horizontal (right-left) directions are defined in accordance with the figures. Nonvolatile memory
100
that is here taken as an example is provided with semiconductor substrate
101
. A plurality of transistor elements
110
are arranged as memory cells on semiconductor substrate
101
in a matrix form in the horizontal direction of the figure and in the direction of depth of the figure.
Transistor elements
110
are separated in the horizontal direction at element separators
102
, element separators
102
having their lower portions buried in the surface of semiconductor substrate
101
and their upper portions protruding from the surface of semiconductor substrate
101
. Source regions
111
and drain regions
112
are formed below the level of the surface of semiconductor substrate
101
at the positions of the transistor elements
110
that are separated by element separators
102
, and gate dielectric film
113
is formed on the surface of semiconductor substrate
101
.
Lower FG
114
are formed on the surface of this gate dielectric film
113
at positions between source regions
111
and drain regions
112
, and upper FG
115
are formed on the surface of lower FG
114
. Source regions
111
and drain regions
112
are formed in the direction of depth of the figure, but lower FG
114
and upper FG
115
are divided into a plurality of sections in the direction of depth of the figure, thereby realizing a configuration in which a plurality of transistor elements
110
are arranged in the direction of depth of the figure.
Interlayer dielectric film
103
is formed between element separators
102
and each of FG
114
and
115
. Upper FG
115
are formed to spread over the surface of interlayer dielectric film
103
with the area of the upper surface of upper FG
115
being greater than the area of lower FG
114
. CG
117
is formed across the horizontal direction of the figure on the upper surface of these upper FG
115
, with ONO (Oxide-Nitride-Oxide) film
116
, which is an intergate dielectric film, interposed.
The upper surface of this CG
117
and the uppermost surface of the above-described configuration formed on semiconductor substrate
101
are protected by isolation layer
104
. In this nonvolatile memory
100
, CG
117
function as word lines and drain regions
112
function as bit lines.
In nonvolatile memory
100
of the above-described configuration, each of a multiplicity of transistor elements
110
arranged in matrix form can store individual bits of data as a memory cell, and moreover, can erase the stored data for prescribed units of a plurality of transistor elements
110
.
In a case in which one part of binary data is written to a particular transistor element
110
, electrons are injected to FG
114
and
115
by applying 0 V to source region
111
, 0 V to drain region
112
, and a voltage of 18 V to CG
117
.
In transistor element
110
in which data are not written at this time, either a voltage of 0 V is applied to CG
117
, or a voltage of 5 V is applied to drain region
112
and source region
111
is made open, whereby the electric field that works on gate dielectric film
113
remains weak and electrons are not injected in FG
114
and
115
.
In a transistor element
110
in which electrons are not injected into these FG
114
and
115
, the cell threshold value is kept at a prescribed erase level, and stored data are therefore maintained at a default value of “0.” In transistor element
110
in which electrons are injected to FG
114
and
115
, on the other hand, the cell threshold value becomes a prescribed write level, whereby, for example, the data “1” are stored.
In above-described nonvolatile memory
100
, the FG is of a two-layered construction of lower FG
114
and upper FG
115
, and CG
117
confronts upper FG
115
without confronting lower FG
114
. Since the upper surface of this upper FG
115
both extends horizontally and is formed with a concave center, CG
117
confronts upper FG
115
over a large surface area. The capacitance between CG
117
and upper FG
115
is therefore great, thus reducing the voltage that must be applied to CG
117
to control the electrons of FG
114
and
115
.
Next, regarding one example of a method of fabricating nonvolatile memory
100
having the above-described configuration, a gate dielectric film and a lower polysilicon film are first grown in that order on the upper surface of semiconductor substrate
101
. Gate dielectric film
113
and lower FG
114
are next formed by removing portions of lower polysilicon film and gate dielectric film so as to divide the lower polysilicon film into a plurality of sections in the horizontal direction.
Source region
111
and drain region
112
are next formed by ion-injecting impurities into semiconductor substrate
101
, and interlayer dielectric film
103
is grown on the surfaces of this semiconductor substrate
101
and lower FG
114
. A trench is formed and insulating material embedded at the position of element isolator
102
of this interlayer dielectric film
103
, and the upper surface of interlayer dielectric film
103
is leveled by CMP (Chemical Mechanical Polishing).
Next, after forming a trench in the surface of lower FG
114
, an upper polysilicon film is formed, and upper FG
115
are formed by removing portions of the upper polysilicon film so as to divide this upper polysilicon film into a plurality of sections. ONO film
116
is then formed on the surface of this upper FG
115
, and an upper conductive film is grown from polysilicon film or tungsten silicide on this surface.
For the purpose of dividing transistor element
110
in the direction of depth of the figure, a photoresist is first applied to the surface of the upper conductive film, a resist mask is formed by patterning this photoresist, and CG
117
is formed by etching the upper conductive film using this resist mask as shown in
Hutchins, Wheeler & Dittmar
NEC Corporation
Wojciechowicz Edward
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