Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-08-11
2002-03-26
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S501000
Reexamination Certificate
active
06363476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiply-add operating device for a floating point number. More particularly, the present invention relates a technique for realizing an improvement in operation efficiency by shortening a critical path for an accumulative adding process of continuous multiply-add operations in a multiply-add operating device which executes a multiply-add operation of floating point numbers by a multiplication process and an addition process for accumulating multiplication results.
2. Description of the Background Art
In recent years, with the rapid spread of multimedia and the spread of video games using advanced GUI (Graphic User Interface) graphics, computer graphic (CG) techniques have been more important. In particular, by the rapid spread of personal computers and video game machines to homes, a demand on a three-dimensional computer graphics (3D-CG) application serving as an application operating on a high-performance processor, especially, a high-quality moving-picture application has been increasing. These CG processes requires an enormous amount of calculation and high calculation performance. Here, a geometrical process in the CG is a phase in which a transformation process or an illumination process of a geometrical graphic model such as coordinate transformation or viewpoint transformation. In these geometrical processes, an inner-product operation is frequently used because a matrix operation and a vector operation are performed. The inner-product operation is frequently used in not only the 3D-CG process described above, but also numerical calculations in conventional scientific and technical calculations. Realization of a multiply-add operating device which perform inner-product operations at a high speed is desired.
The configuration of a conventional floating point multiply-add operating device for performing an inner-product operation will be concretely described below. The configurations of the floating point multiply-add operating device are roughly classified into the following two types.
FIG. 1
shows the first configuration of a floating point multiply-add operating device. In the first configuration, a multiplier and an adder are mounted, and the multiplier and the adder are longitudinally connected to each other, or between which an operation result are bypassed as an operand so as to realize a multiply-add operation.
FIG. 2
shows the second configuration of a floating point multiply-add operating device. In the second configuration, an operating device is not divided into a multiplier and an adder, and a dedicated multiply-add operating device is directly constituted. In a graphic-dedicated machine in which a multiply-add operation occupies a large part of a whole process, the configuration of the second type is often employed. However, in a general MPU (microprocessing unit), the cost of the configuration in which the dedicated operating device is arranged is large. For this reason, the first configuration which is simple and has a good affinity with floating point operating devices in many MPUs is frequently employed.
The details of the processes of the first configuration will be described below. In the following description, it is assumed that all floating point operating devices conform to IEEE754 floating point standards which is operation standards of floating point numbers.
As shown in
FIG. 1
, a floating point multiply-add operating device of the first type is constituted by a multiplication unit
100
and a addition unit
200
. The mantissa operating section of the multiplication unit
100
comprises a multiplication tree
101
, a booth decoder
102
, a final adder
103
, a normalizing circuit
104
, and registers
105
to
109
. The exponent operating section of the multiplication unit
100
comprises two adders
110
and
111
and registers
112
and
115
.
First, the configuration and operation of the multiplication unit
100
will be described below. In the multiplication unit
100
, multiplication of the mantissa of an operand is executed first. Mantissas Fa and Fb of two floating point number operands are multiplied by the booth decoder
102
and the multiplication tree
101
, and the final adder
103
calculates the final product of the mantissas. On the other hand, with respect to exponents, exponents Ea and Eb of two floating point number operands are added to each other by the adder
110
.
Here, the exponents of the operands are subjected to biased representation. For this reason, to be exact, a biased value is subtracted from the sum of exponents calculated as described above to calculate the sum of exponents in the biased representation. In the following description, it is assumed that exponents are subjected to the biased representation.
If carry occurs in the mantissa as a result of the multiplication, normalization is performed. More specifically, a mantissa outputted from the final adder
103
is shifted by only one bit by means of the normalizing circuit
104
. At the same time, an exponent outputted from the adder
110
is incremented by the adder
111
.
FIG. 3
shows a procedure performed when the processes of the multiplication unit
100
are subjected to a pipeline process on two stages (stage X
1
and stage X
2
). Multiplication is executed on the stage X
1
, and final addition and normalization are executed on the stage X
2
. More specifically, on the stage X
1
, the sum of the exponents of operands is calculated to be subjected to biased representation, and a product of mantissas is calculated. In
FIG. 3
, Ei represents a biased value. On the stage X
2
, the exponent of an operand obtained in (1) is incremented, and the final product of mantissas outputted from the final adder
103
is shifted to the right by one bit so as to normalized. The two stages shown in
FIG. 3
indicate an example of a recent typical pipeline process. In
FIG. 3
, shift (X, n, r) represents that X is shifted to the right by n bits.
The configuration and operation of the adder
200
will be described below. The mantissa operating section of the addition unit
200
comprises a shifter
201
for performing alignment of operands Fm and Fn of mantissas, an adder
202
for calculating a sum of mantissas, a normalizing circuit
203
, a preceding 0 detection circuit
204
, and registers
205
to
209
. The exponent operating section of the addition unit
200
comprises two adders
210
and
211
, a selector
212
, and registers
213
to
215
. In the configuration of the addition unit
200
, an addition process is performed according to the steps of: (1) calculation of an alignment shift count; (2) swap; (3) alignment; (4) addition or subtraction; (5) calculation of a normalization number; and (6) normalization.
(1) In the step of calculating an alignment shift count, an alignment shift count representing the number of bits to be shifted to perform alignment of the mantissas Fm and Fn of two operands is calculated. This alignment shift count is calculated as an absolute value of the difference between exponents Em and Ec of the two operands. The calculation of the alignment shift count is executed by the adder
210
.
(2) In the swap step, a large one of the exponents Em and Ec of the two operands is selected as an intermediate value Ed of an addition operation by the selector
212
according to carry of an addition result of the adder
210
. Next ,the mantissas Fm and Fn of the two operands are swapped as needed. Here, of the mantissas Fm and Fn of the two operands, the mantissa of the operand having a small one of the exponents Em and Ec must be input to the shifter
201
to perform alignment.
(3) In the alignment step, on the basis of a result of the calculation of an alignment shift count step (1), the mantissa of an operand having a small exponent is shifted to the right by a necessary number at the shifter
201
, thereby performing alignment.
(4) In the addition or the subtraction, the mantissas of the two operands are added to each other by the adder
202
.
(5) In the
Foley & Lardner
Kabushiki Kaisha Toshiba
Treat William M.
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