Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-11-19
2002-05-14
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S222000
Reexamination Certificate
active
06389505
ABSTRACT:
FIELD OF INVENTION
This invention generally relates to DRAM. In particular it relates to a reduction in the number of refresh actions needed to maintain data in the DRAM.
BACKGROUND
DRAM (Dynamic Random Access Memory) is the lowest cost semiconductor memory available today because it has the smallest viable memory cell. An example of a conventional memory cell comprises a capacitor and a transistor. The capacitor stores electric charge. The quantity of charged stored on the capacitor represents the state of the memory cell, either a zero or a one. Access to the capacitor is governed by a transistor. Through the access transistor, address logic can single-out a memory cell, for a read or write operation, from among an array of cells connected by a common wire called a bitline.
As is well known, even when the access transistor is turned off, a small leakage current trickles through its (drain and source) terminals. Over time, the finite leakage adds or removes enough charge so that it can disturb the state of the memory cell. To prevent that from occurring, the charge stored on the capacitor must constantly be restored, to its nominal value, through a hardware mechanism. A write action is the means by which a fresh state is stored in a DRAM cell. Regardless of whether the write had been issued to refresh the state of the cell or to store a new state in the cell, the net result is the same. The cell state is set to its nominal value, either a “1” or “0”, by a write. After a read, the contents of a DRAM cell must always be restored because the sensing required to detect the cell state also destroys its contents. A destructive read is always followed by a restoring write. The “write-back” stores the data back into the cell that was just read. Every DRAM also has a restore subsystem which periodically sweeps through its entire address space to refresh all its memory cells. Cell banks are inaccessible for a read or write operation during the restoration process. A periodic restore is necessary because some memory cells would not otherwise be restored before they had exceeded the data retention time.
Unfortunately, refresh actions stall other pending requests. It is therefore desirable to minimize the total number of refresh actions so as to maximize the memory bandwidth. Existing DRAM memory cells are typically refreshed after a fixed number of clock cycles regardless of whether those same cells have been restored by means of a read or write action. Thus, the need exists for an improved restore tracking system for DRAM. The present invention addresses such a need.
SUMMARY
In accordance with the aforementioned needs, the present invention includes features for restricting the frequency of refresh operations on a DRAM, by providing a restore tracking system which eliminates the periodic refresh of DRAM entries.
An example of a restore tracking system for reducing a number of refresh actions needed to maintain data entries in a DRAM, in accordance with the present invention comprises: restore tracking means for recording and updating a refresh status of one or more of the data entries in said DRAM; and control logic means, coupled to the restore tracking means, for refreshing one or more of the data entries having an expired status.
In a preferred embodiment of the present invention, the DRAM is used as cache. An example of a restore tracking system for reducing a number of refresh actions needed to maintain data entries in a DRAM integrated within a cache memory including blocks of memory cells which can be refreshed by an external mechanism, comprises: a restore tracking circuit devoted to each block of memory cells for the purpose of tracking a total time elapsed since the block was last restored; wherein the external mechanism includes an external means for triggering a refresh of the block if said restore tracking circuit of the said block reaches a maximum specified data retention time of the DRAM.
The present invention has other features which provide a mechanism for tracking when a memory location was last restored.
The present invention has still other features which provide a timing component, having both discrete and analog embodiments, that can be used in the aforementioned restore tracking mechanism.
The present invention has yet other features for refreshing in a discriminating manner, only those cache entries that have been modified.
The present invention has other features for invalidating in the directory, those data packets whose data will expire, but which exist in duplicate within the memory hierarchy.
REFERENCES:
patent: 5446696 (1995-08-01), Ware et al.
patent: 5684751 (1997-11-01), Manning
patent: 6104658 (2000-08-01), Lu
patent: 6134167 (2000-10-01), Atkinson
patent: 6222785 (2001-04-01), Leung
patent: 6230235 (2001-05-01), Lu et al.
patent: 6230274 (2001-05-01), Stevens et al.
patent: 6269039 (2001-07-01), Glossner, III et al.
Emma Philip George
Reohr William Robert
Wang Li-Kong
Chace Christian P.
Ellis Kevin L.
International Business Machines - Corporation
Tassinari, Jr. Robert P.
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