Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
1999-06-09
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S314000, C438S316000, C438S687000, C257S751000, C257S752000
Reexamination Certificate
active
06395607
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of microelectronic devices such as integrated circuit structures. More particularly, the invention relates to microelectronic devices having a self aligned metal diffusion barrier.
2. Description of the Related Art
The production of microelectronic devices requires multilevel wiring interconnects regions within the devices. In forming such structures, it is conventional to provide a substrate having first level wiring lines, an interlayer dielectric (ILD) and then second level wiring lines. One or more interconnections are typically formed between the first and second level wiring lines. Openings are formed in the dielectric layer which are filled with a metal to form a metal plug interconnect. After the two level interconnect structure is formed, it is necessary to provide another interlevel dielectric (ILD) layer to accommodate further processing of the integrated circuit device. The intermetal dielectric layer usually consists of a layer of a dielectric and an oxide such as silicon oxide which is deposited by plasma enhanced chemical vapor deposition or other processes. When the damascene approach is taken for forming integrated circuits with copper interconnections, the conventional fabrication method requires a layer of silicon nitride film on top of the copper interconnection to prevent upward copper diffusion into the ILD. However, the use of silicon nitride has two major disadvantages. It has a high dielectric constant and thus degrades speed and performance resulting from increased in-line and inter-level capacitance. This speed degradation becomes unacceptable for integrated circuits fabricated using 0.18 &mgr;m and more advanced technologies. Silicon nitride acts a copper diffusion barrier over the copper interconnects, however its use involves other problems. Part of the silicon nitride over the copper interconnects has to be removed during via etch so that a conductive path can be established between two neighboring interconnect levels through vias. Anisotropic plasma etch is usually used for opening vias. The common practice is performing an over-etch in the vias to assure that the underlying copper is fully exposed. During this over-etch, some of the copper is backsputtered and deposited on via sidewalls or re-deposited on the copper interconnects. During sputter etching, deposition of back-sputtered copper on via sidewalls takes place. Copper deposited on via sidewalls can readily diffuse through the ILD and eventually results in an electrical short between two adjacent interconnects thus causing major reliability problems. The causes of these problems is the use of silicon nitride, a dielectric, as a diffusion barrier as well as the simultaneous exposure of copper and the ILD during plasma etches or sputter etches. According to the invention, these problems are solved by use of a conductive, i.e. a metallic diffusion barrier instead of silicon nitride. The same metal barrier as is commonly used on the sides and at the bottom of a copper interconnect may be deposited on top of the copper interconnect.
SUMMARY OF THE INVENTION
The invention provides a process for forming a microelectronic device which comprises:
(a) forming a first dielectric layer on a substrate;
(b) forming a trench having inside walls through the first dielectric layer;
(c) lining the inside walls of the trench and covering a top of the first dielectric layer with a first layer of a barrier metal;
(d) filling the trench with a fill metal and covering the top of the first layer of the barrier metal with a layer of the fill metal, wherein the fill metal and the barrier metal have substantially different removal selectivities;
(e) removing the layer of the fill metal from the top of the first layer of the barrier metal and forming a recess in the fill metal in the trench extending to a level below the top of the first layer of the barrier metal on the first dielectric layer;
(f) filling the recess with the barrier metal and optionally depositing a second layer of the barrier metal onto the top of the first layer of barrier metal;
(g) removing the optional second layer of barrier metal from the top of the first dielectric layer and leaving the barrier metal in the recess such that the barrier metal in the recess conforms to the top of the underlying fill metal in the trench;
(h) depositing a second dielectric layer onto the first dielectric layer and onto the barrier metal in the recess.
The invention also provides a microelectronic device comprising a substrate, a dielectric layer on the substrate; a trench having inside walls through the dielectric layer; a lining of a barrier metal on the inside walls of the trench; a fill metal in the trench between the linings on the inside walls of the trench, wherein the fill metal and the barrier metal have substantially different removal selectivities; a covering of the barrier metal on the fill metal, which covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.
REFERENCES:
patent: 5262354 (1993-11-01), Cote et al.
patent: 5527739 (1996-06-01), Parrillo et al.
patent: 5592024 (1997-01-01), Aoyama et al.
patent: 5801095 (1998-09-01), Yew et al.
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6110648 (2000-08-01), Jang
Allied-Signal Inc.
Le Dung A
Nelms David
Roberts & Mercanti LLP
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