Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-30

2002-07-02

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

C365S189050, C365S230080, C365S233100

Reexamination Certificate

active

06414879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a DRAM type semiconductor memory device which has an asynchronous SRAM type interface in which a command is received and a corresponding operation is started.
2. Description of the Related Art
Recently, a compact mobile terminal such as a cellular phone has collaborated with the Internet and handled a large amount of data. This has stimulated a large-capacity memory. Nowadays, an SRAM (Static Random Access Memory) is employed in the cellular phones because of its low power consumption. However, the SRAM does not have a high integration density. The larger the SRAM capacity, the more expensive the cost. In contrast, the DRAM is a low-cost, high-capacity memory. The DRAM and SRAM do not have different command systems. This does not allow the SRAM to be simply interchanged with the DRAM. In this case, a major problem arises from the timing at which write data is input. In the DRAM, write data is latched based on the start of a write cycle (at this time, a chip enable signal /CE and a write enable signal /WE fall). In the SRAM, write data is latched based on the end of the write cycle (at this time, the chip enable signal /WE and the write enable signal /WE rise).
FIG. 1
is a timing chart of a data write operation in which data is written into an SRAM. After the chip enable signal /CE (not shown) falls, an address add is latched in synchronism with the falling edge of the write enable signal /WE, and write data DQ is latched in synchronism with the rising edge of the write enable signal /WE. If the DRAM is operated in the same manner as shown in
FIG. 1
, the current write operation may extend to the next command cycle. Thus, if the read command is followed by a write command, the read operation will start with a delay. This delays outputting of data. In order to avoid this problem, a late-write system has been proposed.
FIG. 2A
is a timing chart of the latewrite system,
FIG. 2B
is a circuit diagram of an address latch circuit provided in the DRAM, and
FIG. 2C
is a circuit diagram of a data latch circuit provided therein.
The address latch circuit shown in
FIG. 2B
latches an address ADD supplied from the outside of the DRAM, and includes a buffer
10
, gates
11
,
12
and
13
, a latch
14
, and an inverter
15
. Each of the gates
11
-
13
is made up of a transfer gate and an inverter. The buffer
10
includes a latch
10
a
and an inverter
10
b.
The data latch circuit shown in
FIG. 2C
latches data DQ supplied from the outside of the DRAM, and includes a buffer
16
, gates
17
and
18
, and an inverter
16
a.
The write operation starts in synchronism with the falling edge of the write enable signal /WE. A write command wrpz, which is generated by a command decoder that is not shown for the sake of simplicity, is applied to the address latch circuit shown in FIG.
2
B and the data latch circuit shown in FIG.
2
C. In response to the write command wrpz, address A
0
, which has been latched in the buffer
10
in the previous write cycle, passes through the gate
12
and the latch
14
. The output signal of the latch
14
is an internal address iaz. In response to the above write command wrpz, data D
0
, which has been latched in the buffer
16
in the previous write cycle, passes through the gate
18
. The output signal of the gate
18
is an internal write signal wdbz. Next, a write address latch signal walz causes address A
1
to be latched in the buffer
10
via the gate
11
. A write data latch signal wdlz is generated from the rising edge of the write enable signal /WE. The signal wdlz causes write data D
1
to be latched in the buffer
16
. In the write cycle, the write data D
0
is written into a cell specified by the write address A
0
, and simultaneously the write address A
1
and the write data D
1
are respectively latched in the buffers
10
and
16
. A write address waz latched in the buffer
10
changes from A
0
to A
1
, and write data wdz latched in the buffer
16
changes from DO to D
1
. Similarly, in the next write cycle, write data D
1
is written into a cell specified by address A
1
, and simultaneously next write address A
2
and write data D
2
are respectively latched in the buffers
10
and
16
.
In a read operation, the address ADD latched by a read command rdpz is output from the address latch circuit as the internal address iaz. That is, the read address is not latched in the buffer
10
.
As described above, the late-write system enables write data to be written in the next write cycle. Thus, even when the read command follows the write command, the corresponding read operation can start without a considerable delay, so that data can be output promptly.
The SRAM has a state in which /CE=L (low level), /WE=H (high level), and /OE (output enable signal)=H. This state is called an output disable state. As shown in timing charts of
FIGS. 3A and 3B
, the SRAM is set to the write state when the write enable signal /WE falls in the output disable state (FIG.
3
B), and is set to the read state when the output enable signal /OE falls in the output disable state (FIG.
3
A). As has been described previously, the late-write system uses different addresses in the read and write operations. More particularly, the read operation uses the latched read address as it is. In contrast, the write operation uses the write address that was latched in the immediately previous write cycle. Thus, the device is set to the write state when the write enable signal /WE falls in the output disable state, and is set to the read state when the output enable signal /OE falls in the output disable state.
Generally, the access time in the read operation from the output disable state is defined so as to be shorter than that of the normal read operation in which the output enable signal /OE is L and the Chip enable signal /CE falls. Therefore, it is too late to start the read operation after the output enable signal /OE switches to L, so that data cannot be output in time.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device in which data can be read from the output disable state more quickly.
The above objects of the present invention are achieved by a semiconductor memory device of a dynamic type having an interface of a static-type semiconductor memory device, comprising: a memory cell array; and a control circuit controlling a read operation to be initiated in response to a predetermined signal externally applied thereto before a read or write command is externally applied to the control circuit.
The above objects of the present invention are also achieved by A semiconductor memory device of a dynamic type having an interface of a static-type semiconductor memory device, comprising: an address latch circuit that latches an external address; and a command decoder that controls the address latch circuit to latch the external address when receiving a predetermined signal externally supplied before a write command or a read command is externally applied to the semiconductor memory device.


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patent: 5392239 (1995-02-01), Margulis et al.
patent: 5668760 (1997-09-01), Hazen
patent: 5912847 (1999-06-01), Tamaki
patent: 6144616 (2000-11-01), Suzuki et al.
patent: 6151268 (2000-11-01), Yoshikawa
patent: 6175535 (2001-01-01), Dhong et al.
patent: 6243279 (2001-06-01), Maesako et al.

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