Method of forming insulating spacers in DRAM chips

Details Method of forming insulating spacers in DRAM chips Method of forming insulating spacers in DRAM chips

2000-06-30

2002-01-29

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S738000

Reexamination Certificate

active

06342450

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. The formation of insulating spacers is essential in the fabrication of such metal contacts to prevent any gate conductor/source electrical short that would be detrimental to the DRAM chip reliability.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits and particularly in dynamic random access memory (DRAM) chips, the one-device memory cell is comprised of an array transfer transistor, typically an insulated gate field effect transistor (IGFET) and a storage capacitor. For each IGFET, the source is connected to a metal contact which is part of a bit line, the drain is connected to one electrode (node) of the storage capacitor and the gate conductor is the word line (runs orthogonal to the bit line). It is of paramount importance to make sure that there is no electrical short between the metal contact with the source region and the gate conductor. As a matter of fact, a total and reliable isolation is essential to the IGFET integrity and thus to the memory cell operation. Typically, the gate conductor consists of a polycide, i.e. a composite metal silicide/doped polysilicon structure (the preferred metal is tungsten so that the metal silicide has a WSix like formulation). This isolation is performed by a dedicated dielectric layer, usually of silicon nitride (Si
3
N
4
), which forms an insulating spacer on the gate conductor (GC) sidewall.
In the last generation of DRAM chips, due to scaling reduction effects, the process window is constantly reduced and consequently, there is a serious risk of exposing said gate conductor sidewall during the formation of the contact hole to expose the source region. Recently, a new contact hole structure named “borderless” and processes of efficiently making the same were developed in the semiconductor industry. These techniques are necessary to meet the modern reliability requirements of this industry to date. The new borderless contact hole structure requires the deposition of an oxynitride film which will be used as an etch stop and a barrier layer during the source contact hole formation. As a result, the gate conductor (word line) that was previously only laterally coated by said dedicated dielectric layer to form the insulating spacer is now totally encapsulated by said oxynitride layer to prevent any undesired exposition of the gate conductor when the contact hole exposing the source region is opened during subsequent photolithography and etch steps. Finally, the borderless contact hole is filled with a metal such as tungsten, to produce the so-called borderless metal (CB) contact.
Therefore, the production of borderless metal contacts is an absolute requirement for the 64 Mbits DRAM chips and follow-on generations. However, the fabrication process of a borderless metal contact represents a major challenge because it must: (1) ensure the lowest possible electrical resistance with the source region and (2) present none risk of a potential source region/gate conductor electrical short that would be detrimental to the DRAM chip functionality. In addition, a borderless metal contact must be formed according to a simple and affordable fabrication process.
A conventional borderless metal contact (CB) fabrication process including the insulating spacer formation is described hereinbelow in conjunction with FIG.
1
and
FIGS. 2A-2F
. All processing steps are conducted in the so-called MEOL module (MEOL stands for Middle End Of the Manufacturing Line). It is important to point out that the illustrated layers in the drawings are not necessarily drawn to scale.
FIG. 1
schematically illustrates the initial structure referenced
10
which basically consists of a P-type doped silicon substrate
11
coated with a 4.5 nm thick silicon oxide (SiO
2
) gate layer
12
. In the substrate
11
, two storage capacitors in their respective trenches are shown. On said SiO
2
gate layer
12
, a composite insulating/conductive/insulating film has been formed. For instance, it is comprised of a bottom 100 nm thick phosphorus doped polysilicon layer
13
, a 55 nm thick tungsten silicide (WSix) layer
14
, and a 200 nm thick silicon nitride (Si
3
N
4
) capping layer
15
. After thermal treatments, the doped polysilicon and the tungsten silicide form a layer
13
/
14
of the polycide material mentioned above. Gate conductor (GC) lines
16
are formed by patterning these three layers using a conventional dry etch process, so that each gate conductor line
16
includes a Si
3
N
4
cap still referenced
15
. Finally, a 14 nm thick thermal oxide layer
17
laterally passivates the polycide layer
13
/
14
to prevent any spurious oxidation during the following thermal steps. As apparent in
FIG. 1
, there is shown a diffusion region
18
, typically the source of an IGFET.
Now, referring to
FIG. 2A
, the conventional borderless metal contact fabrication process starts with the conformal deposition by LPCVD of a Si
3
N
4
layer
19
having a thickness of about 30 nm onto the structure
10
top surface. For instance, the Si
3
N
4
material of layer
19
can be deposited in a TEL Fast Thermal Ramp, a tool manufactured by TOKYO ELECTRON LTD, Tokyo, Japan using a NH
3
/DCS (dichlorosilane) chemistry and the process parameters recited below.
Pressure:
150 mTorr
Temperature:
780° C.
NH
3
Flow:
250 sccm
DCS flow:
50 sccm
Duration:
16 min
The target is to obtain this thickness of about 30 nm both on the top and the sidewall of gate conductor lines
16
(measured on a product wafer).
After Si
3
N
4
material deposition, an anisotropic dry etching step is then performed to form the Si
3
N
4
spacers. The etch step is stopped as soon as the SiO
2
gate layer
12
top surface is exposed. For instance, this step may be conducted in the MxP+ chamber of an AME 5200 tool, commercially available from Applied Materials, Santa Clara, Calif., USA, for instance, with the following operating conditions:
Pressure:
50 mTorr
Power:
100 W
Temp. (Wall/Cath.):
15/15° C.
He Cooling:
26 Torr
CHF
3
Flow:
28 sccm
O
2
Flow:
6 sccm
CO
2
Flow:
75 sccm
Ar Flow:
50 sccm
Duration:
75 s
Spacers referenced
19
are shown in FIG.
2
B.
This dry etch step is monitored in-situ by an optical etch endpoint technique (N
2
line) using an optical emission spectrometer. When the surface of the SiO
2
gate layer
12
between the gate conductor lines
16
is reached, the etching is stopped. Because of inherent characteristics of the Si
3
N
4
deposition step described by reference to
FIG. 2A
, Si
3
N
4
layer
19
is thicker at wafer edge than at wafer center inducing thereby a significant thickness non-uniformity across the wafer. Moreover, because of inherent characteristics of the Si
3
N
4
etch step described by reference to
FIG. 2B
, this non-uniformity is further increased due to a higher etch rate at the wafer center than at the wafer edge. As a consequence, the SiO
2
gate layer
12
surface is reached first at wafer center. Therefore, a large overetch is required to avoid Si
3
N
4
residues remaining onto the SiO
2
gate layer
12
at the wafer edge. During this Si
3
N
4
layer
19
overetch step, Si
3
N
4
cap
15
is eroded at wafer center inducing thereby a large range on the Si
3
N
4
cap
15
thickness across the wafer surface. After overetch, it is essential that SiO
2
gate layer
12
remains above the diffusion regions
18
that are exposed as illustrated in
FIG. 2B
without Si
3
N
4
residues at the bottom corner of the Si
3
N
4
spacer
19
and without an erosion at the Si
3
N
4
cap
15
top corner. SiO
2
gate layer
12
remains after Si
3
N
4
layer
19
etch thanks to a chemistry that has a Si
3
N
4
etch rate two times faster than the etch rate.
At this stage of the CB formation process, the wafer is submitted

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