Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-03-02
2002-01-29
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S041000
Reexamination Certificate
active
06342792
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic integrated circuit devices (“PLDs”), and more particularly to improved circuitry for the logic modules of such devices.
Programmable logic devices typically include (1) many modules of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic modules. Each logic module is programmable to perform any of several different, relatively simple logic functions on input signals applied to that logic module to produce one or more logic module output signals. For example, a logic module may include combinatorial logic circuitry such as a look-up table that is programmable to produce a first intermediate signal that is any logical combination of several input signals applied to the logic module. The logic module may also include a register that is capable of registering the first intermediate signal to produce a second intermediate signal. The logic module may still further include programmable logic connector (“PLC”) circuitry that is programmable to select one or more logic module output signals from the first and second intermediate signals of the logic module. Although each logic module may thus be able to perform only a relatively small logic task, the interconnection resources of the PLD allow any number of the available logic modules to work together to perform very complex logic tasks.
Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. Pat. No. Re. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. Pat. Ser. No. 6,215,326, all of which are hereby incorporated by reference herein in their entireties.
In some PLD designs the logic modules can respond more rapidly to some of their input signals than to others of those signals. If that is the case, then it is advantageous to apply signals that are available relatively early in an operating cycle of the PLD to the logic module inputs to which the logic module responds more slowly, and to apply signals that are only available later in the operating cycle to the logic module inputs to which the logic module responds more rapidly. Some PLDs have interconnection resources that allow any signal in those resources to be applied to any input of a logic module so that relatively fast (i.e., early) and relatively slow (i.e., late) signals can be appropriately routed to the slow and fast inputs, respectively, of each logic module. To speed up signal propagation through interconnection resources, however, it may be desirable to make those resources somewhat less flexible with regard to possible signal routings (e.g., to reduce the number of PLCs that are connected to various interconnection conductors and to thereby reduce the loading on those conductors). While this has the benefit of speeding up the interconnection resources, it may make it more difficult or even impossible in some cases to route fast and slow signals, respectively, to the slow and fast inputs of various logic modules. This in turn makes the speed characteristics of the logic modules even more critical to the overall speed performance of the PLD.
In addition to the foregoing, enhancements to the capabilities of logic modules are always being sought. For example, it is known to allow one of the inputs to a logic module to be selectively applied to the register of the logic module in lieu of the first intermediate signal from the combinatorial logic circuitry of the module. This is sometimes known as “lonely register mode” operation of the logic module. This type of operation tends to separate the two parts of the logic module (i.e., the combinatorial logic circuitry and the register) from one another from a logical or operational standpoint, and it would be desirable to tie those two parts together more closely in lonely register mode. It would also be desirable to facilitate the interconnection of the registers in several logic modules in a series (e.g., to facilitate the provision of shift-register-type capabilities), without making the combinatorial logic of those logic modules unavailable for other uses.
In view of the foregoing, it is an object of this invention to provide improved logic module circuitry for PLDs.
It is a more particular object of the invention to provide logic module circuitry for PLDs that can be made to operate more rapidly and that is less dependent on possible differences in input signal timing for such rapid operation.
It is still another object of the invention to provide logic module circuitry for PLDs that enhances lonely register mode operation of the logic module and/or that facilitates connecting the registers of multiple logic modules in series in the manner of a shift register.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing logic module circuitry for PLDs that may include the capability of swapping at least some of the input signals applied to the logic module. The input signals that can thus be swapped by a logic module are preferably among those for which swapping by the interconnection resources that supply signals to the logic module would be difficult or impossible. The input signals that can thus be swapped are also preferably among the signals that the logic module is capable of processing most rapidly. These are the signals that can be the most critical to rapid operation of the logic module, and so it is of the greatest benefit to have the greatest flexibility with regard to how these signals are routed.
As an alternative or addition to the abovementioned signal swapping capability, additional drivers may be included at relatively downstream points in the circuitry of a logic module to increase the operating speed of the logic module and in some embodiments to also effectively increase the number of logic module inputs that the logic module can process at relatively high speed. This also helps to reduce the sensitivity of the logic module to inflexibilities in the signal routing capabilities of the associated interconnection resources.
As still other alternatives or additions to the foregoing, each logic module may include programmable circuitry for allowing one of the input signals to the logic module to be applied substantially directly to the register in that logic module in lieu of the output signal of the combinatorial logic circuitry of that logic module, and also for allowing the output signal of the register to take the place of the just-mentioned one input signal as one of the inputs to the combinatorial logic circuitry. This significantly enhances “lonely register mode” operation of the logic module. Interconnections may also be provided between logic modules for allowing the output signal of the register in each logic module to be applied substantially directly to the register in another register in a shift-register-type arrangement of the registers which does not preclude use of the associated combinatorial logic circuitry for other purposes.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: RE34363 (1993-08-01), Freeman
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5432719 (1995-07-01), Freeman et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5999015 (1999-12-01), Cliff et al.
Device Data Book, 1999, Altera Corporation, San Jose, California, pp. 25-88 (“Apex 20K Programmable Logic Device Family”, May 1999, ver. 2); pp. 89-345 (“Flex 10K Embedded Programmable Logic Family Data Sheet”, May 1999, and “Flex 10KE Embedded Programmable Logic Family Data Sheet”, May 1999, ver. 2); and pp. 347-410 (“Flex 8000 Programmable Logic Device Family Data Shee
Huang Wei-Jen
Ngai Tony
Pedersen Bruce
Shumarayev Sergey
Altera Corporation
Court Andrew Van
Fish & Neave
Jackson Robert R.
Tokar Michael
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