Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-03-26
2002-05-21
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06392918
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for generating a reference voltage for reading and evaluating read signals that are read from memory locations of a ferroelectric memory with a constant plate voltage via bit lines. The circuit configuration has a reference voltage device and a selection and evaluation device that is connected to the bit lines.
In dynamic read/write access memories (DRAMs) a read signal lies above or below a reference level. In this example, a voltage value is larger than VREF for “1” and smaller than VREF for “0”. The generation of the reference signal VREF with 0 V or nearly 0 V is relatively simple here.
In ferroelectric memories (FeRAM), the relations are more complicated than this. Both the read signal for “1” and that for “0” are greater than 0 V and have a characteristic of the voltage relative to time. Because the characteristics of the two read signals for “1” and “0” run in the same direction, it is more difficult than in DRAMs to generate a reference signal VREF that is always midway between “0” and “1”.
Initially, in order to solve this problem, double locations (what are known as 2T2C locations) were used in FeRAMs, which consist of two locations, each having a transistor and a capacitor. In a first location, the signal to be stored is written, whereas the complementary signal is entered into a second location. Both locations are then available in the readout. The disadvantage of this procedure is that a relatively large area is consumed, but, the noise interval is reduced as a result of what is known as the “imprint” effect.
The problem of a large consumption of space per se can be solved by single locations (1T1C-locations) having one transistor and one capacitor. The 1T1C locations can thus achieve basically the same storage density as in DRAMs, though they require a reference location for generating the reference signal (see the reference by H. Koike et al., titled “A 60 ns 1-Mb Nonvolatile Ferroelectric Memory with a Nondriven Location Plate Line Write/Read”, IEEE J. Of Solid-State Circuits, Vol. 31, Nr. 11, November 1996: pp. 1625-1634). If the known 1T1C location is used the same way as the locations of DRAMs, the location capacity of the reference location must be configured differently than the location capacity of the actual memory location. This is disadvantageous, however, because it requires a fine adjustment of the location capacity in order to obtain an exact reference voltage VREF as the actual arithmetic mean of the two voltages V
1
and V
0
for “1” and “0”, which always gives rise to read signal losses at an evaluator due to fluctuations in the technology and other influences. This is undesirable above all given low supply voltages. Likewise, various aging effects of the memory location and the reference location can be disadvantageous.
These disadvantages are avoided in another solution of the above problem (see the reference by H. Hirand, titled “2V/100 ns 1T/1C Non-Volatile Ferroelectric Memory Architecture with Bitline-Driven Read Scheme . . . ”, IEEE J. of Solid-State Circuits, Vol. 32, Nr. 5, May 1997: 649-654), in which aging of the memory location is prevented by always keeping it in a non-polarized state at 0 V. This is accomplished in that a specific set voltage is specified when the reference location is reset. But in this case the precision of the achievable reference voltage is dependent upon the set voltage and its temperature response.
Generally, in the read process in ferroelectric memories a location in the form of a capacitor having a ferroelectric dielectric, for instance composed of bismuth barium tantalate (WBT) or lead zirconium titanate (BZT), is connected to a selection transistor by way of a bit line. On the basis of the relations of the capacitors, the payload signal that emerges on the bit line is on the order of 100 mV. This relatively small payload signal is amplified in a read amplifier to the full logic level for “1” or “0”. However, as mentioned above, the read amplifier requires the reference voltage, which should ideally represent the mean value of the voltages that are obtained in the readout of a “0” and a “1” from a memory location.
It is possible to generate such a reference voltage VREF by reading two reference locations that contain inverse information on a bit line pair. The arithmetic mean of the two previously obtained read signals is then formed by subsequently shorting the bit line pair. The reference signal is left on one of the two bit lines, while the memory location that will be read is activated on the other bit line. Next, the voltage that has been read is compared in the read amplifier to the reference voltage and amplified to the full logic level.
This kind of procedure does permit a relatively precise generation of a reference signal; however, it requires a relatively long time as a result of the serial sequence of the generation of the individual signals.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for generating a reference voltage for reading a ferroelectric memory that overcomes the above-mentioned disadvantages of the prior art devices of this general type, wherein the reference voltage can be provided at a precise level despite a shortened read cycle.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration containing a ferroelectric memory having memory locations supplied with a constant plate voltage. A first bit line pair formed of bit lines each connected to one of the memory locations, is provided. A selection and evaluation device is connected to the bit lines of the first bit line pair. A second bit line pair formed of bit lines is provided. Selection transistors are provided and each have a first terminal connected to the selection and evaluation device and a second terminal connected to one of the bit lines of the second bit line pair. A reference voltage device is provided and has two reference locations that can be charged with complementary signals and read into the selection and evaluation device simultaneously for generating a reference voltage for reading and evaluating read signals read from the memory locations. Each of the two reference locations is connected to one of the bit lines of the second bit line pair and can be read to the selection and evaluation device through a corresponding one of the selection transistors.
The object is inventively achieved in a circuit configuration of the above described type in that the reference voltage device contains two reference locations that can be charged with complementary signals and read simultaneously into the selection and evaluation device in order to generate the reference voltage.
Thus, the two reference locations are used simultaneously in the inventive circuit configuration. These two reference locations are precharged to “1” or “0” via two lines prior to the beginning of the read process, so that a voltage corresponding to “1” is stored in one reference location, and a voltage corresponding to “0” is stored in the other reference location. The two reference locations are then output simultaneously onto one reference bit line at the beginning of the read process, so that it sets a precise reference voltage on the reference bit line. In a preferred embodiment, the restoring of “1” and “0” to the reference locations can be accomplished by way of separately provided supply lines.
Another preferred embodiment of the invention provides that the reference locations can be recharged via the bit lines themselves given the implementation of appropriate wiring measures. Each reference location can be connected to each of the two bit lines of the pair by way of a respective selection transistor that is controlled by a word line.
In another advantageous development of the invention, the two reference locations are connected to an additional bit line pair and can be read to the selection and evaluation device via respective
Braun Georg
Hoffmann Kurt
Hönigschmid Heinz
Kowarik Oskar
Röhr Thomas
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phan Trong
Stemer Werner H.
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