Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-02-09
2002-03-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S073000, C326S081000, C327S538000, C327S540000
Reexamination Certificate
active
06353335
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to compensating circuits incorporated into micro-electronic complementary metal-oxide semiconductor (hereinunder “CMOS”) integrated circuits (“IC”s), of the type used in Pseudo
Emitter Coupled Logic receivers (hereinafter “PECL-rx”). More particularly, the present invention relates to improvements in the design of the output buffer portion of such circuits which can result in increased production yield and/or lower rejection rate of ICs incorporating these circuits, as well as to ICs incorporating the improvements.
PECL-rx are the subject of various US and other patents, e.g. U.S. Pat. No. 5,963,053 to Amar Manuhar et al., U.S. Pat. No. 5,994,923 to Mohammad J. Navabi.
A known basic PECL-rx circuit comprises three blocks: a pre-amplifier, which will not be referred to any further, a decision stage and an output buffer. The output buffer comprises a Complementary Self-bias Differential Amplifier, hereinbelow a “CSDA”. The CSDA comprises two inverters, each inverter comprising one p-type field effect transistor (“transistor” hereinafter) connected in series to one n-type transistor, as is known, The CSDA has one output: V
out
, and two inputs: +V
0
and −V
0
. The values of the inputs +V
0
, −V
0
must be close to the trip point of the CSDAs: +V
0
being above the trip point and −V
0
below it, and sufficiently far away from their saturation zones.
Experience with PECL-rx IC's shows that it is difficult to obtain a satisfactory yield of IC's incorporating PECL-rx circuits due to the inherent sensitivity of the CSDA to the process. However, a marked increase in yield of acceptable or process adaptive IC's incorporating this invention is achieved.
ICs are complex electronic circuits made on a small, single piece of wafer and are comprised of numerous, microscopic electronic components. The number of components in many ICs which are currently produced can reach many millions on several square cms.
During the IC manufacturing process, several materials are successively applied to the wafer, which is typically several hundreds of microns thick and can be a few hundred mm's in diameter. Many ICs can be manufactured from one wafer either in the form of layers deposited on top of each other, for example, as oxidized layers or surfaces, or as materials selectively applied to parts of the IC wafer. Additionally, portions of these layers may be treated, for example, by making a mask based on the layer design and masking parts of the relevant layer with the specific mask work, then etching, in order to controllably remove some portion of them, thereby leaving a desired pattern of etched layer on top of lower layers. Another process which may be applied to some of the layers is doping. That is the addition into a particular layer's material of low concentrations of other materials which affect the electrical properties of the doped material. The resultant patterns of the various layers, when superimposed on each other, form miniature electric and electronic components such as resistors, capacitors, transistors and the like which together comprise the IC. Variations in any and all of the above steps can introduce variability which can affect the voltage input to the CSDA, thereby affecting the trip point and consequently the CSDA voltage may be out of the desired range.
Several different technologies of IC's exist. According to each one of these technologies, IC's are manufactured from several layers of different materials. Still different materials are used to manufacture each one of the various technologies of IC's. Also, the manufacturing of each one of the different layers of an IC calls for a different technology. Each one of the various ICs technologies offers certain advantages and suffers from some disadvantages. This invention relates to ICs of CMOS (“complementary metal oxide semiconductor”) technology and in particular to the production of an improved complementary self-bias differential amplifier which is not sensitive to the process, as are currently known CSDAs.
The factors in the process which can affect the CSDA include all of the nominal physical and chemical properties of the components of the IC, the net effect of these properties, the temperature under which the CSDA is operating, as well as the supply of voltage into the circuit.
Agreed upon testing methods using the corner conditions, to be explained below, are applied which determine the acceptability of an IC. Those ICs that pass the agreed upon tests are considered acceptable, while those which fail are rejected.
Especially in an industry with ever-increasing competition, it is of major economic significance for the IC manufacturer to increase its yield, or the fraction of acceptable ICs out the total number of the produced ICs. Alternatively, the lowering of the fraction of rejects or rejected ICs within a production lot can be economically very rewarding.
SUMMARY OF THE INVENTION
It is one objective of the present invention to provide an additional, auxiliary electronic circuit incorporated into PECL-rx IC's, so that its trip point is adjusted without markedly increasing the IC's complexity.
It is a further objective of the present invention to increase the yield, or the percentage of acceptable ICs incorporating PECL-rx, among the total number produced.
These objectives and others not specifically enumerated are achieved according to this invention by incorporating into the PECL-rx a negative feedback loop comprising an inverter which serves as a correcting circuit.
REFERENCES:
patent: 4763026 (1988-08-01), Tsen et al.
patent: 4998026 (1991-03-01), King
patent: 5087834 (1992-02-01), Tsay
patent: 5495184 (1996-02-01), Des Rosiers et al.
patent: 5614843 (1997-03-01), Mita et al.
patent: 5633602 (1997-05-01), Sanwo et al.
patent: 5666069 (1997-09-01), Gibbs
patent: 5963053 (1999-10-01), Manohar et al.
patent: 5994923 (1999-11-01), Navabl
patent: 7297704 (1995-11-01), None
Chirnomas Morton
Conexant Systems Inc.
Paik Steven S.
Tokar Michael
LandOfFree
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