Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-09-13
2002-01-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S201000
Reexamination Certificate
active
06335876
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method of testing the same and, more particularly, to removal of remanent polarization in a ferroelectric memory.
A ferroelectric memory relevant to the present invention is shipped after being subjected to testing and package assembly through steps as shown in FIG.
13
.
In step S
10
, semiconductor chips are fabricated in units of semiconductor wafers. In step S
12
, the semiconductor wafers are tested one by one. In step S
16
, the wafers are diced to package/assemble chips. In step S
18
, a final product test is conducted. In step S
22
, the products are shipped.
In the tests in steps S
12
and S
18
, writes and erases to ferroelectric capacitors are performed.
In this method, however, the testing steps are completed with polarization remaining in ferroelectric capacitors. When the flow advances to the subsequent steps in this state, the characteristics of the ferroelectric capacitors deteriorate by thermal history. This reduces the data read amount and causes a phenomenon so-called imprint.
For example, in the package assembly step instep S
16
,after semiconductor chips are encapsulated with resin, heat of about 170 to 200° C. is applied for about 1 hr. In this step, a ferroelectric capacitor in which polarization remains causes imprint and deteriorates its characteristics. This shortens the life of the capacitor as a product.
Also, when a memory is shipped with polarization remaining in a ferroelectric capacitor, imprint occurs if careless thermal history is applied during storage before actual use. This shortens the product life after that. In this method relevant to the present invention as described above, the testing steps are completed while polarization produced by write operations during these steps remains. This remanent polarization degrades the characteristics and shortens the product life.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory and a method of testing the same, which can prevent deterioration of the characteristics and shortening of the product life caused by remanent polarization in testing steps.
A semiconductor memory testing method of the present invention is a method of testing a semiconductor memory having a memory cell including a ferroelectric capacitor, comprising a second write testing for the semiconductor memory, and removing remanent polarization such that an absolute value of polarization remaining in the ferroelectric capacitor is smaller than an absolute value of polarization remaining in normal operation.
In this method, the remanent polarization removing step can comprise writing identical data in all memory cells, and setting, in a block from which remanent polarization is to be removed, a bit line connected to the memory cells at a predetermined voltage and applying a remanent polarization removing plate line voltage lower than a voltage in normal write operation to a plate line connected to the memory cells, and the remanent polarization removing plate line voltage can be substantially equal to or higher than a coercive voltage of the ferroelectric capacitor.
A semiconductor memory of the present invention comprises a cell array in which a plurality of memory cells each including a ferroelectric capacitor are arranged, and a write circuit for writing data in the memory cells, the write circuit removing polarization remaining in the ferroelectric capacitor by applying a voltage lower than a voltage in normal operation to a plate line connected to the memory cell, such that an absolute value of polarization remaining in the ferroelectric capacitor is smaller than an absolute value of polarization remaining in normal operation.
Another semiconductor memory of the present invention comprises a cell array in which a plurality of memory cells each including a ferroelectric capacitor are arranged, a plate line driver for applying a supplied voltage to a plate line connected to the memory cells, a plate line voltage generating circuit for generating a remanent polarization removing plate line voltage lower than a normal operation plate line voltage, and a switching circuit for selectively supplying, to the plate line driver, one of the normal operation plate line voltage given and the remanent polarization removing plate line voltage generated by the plate line voltage generating circuit, wherein when performing a normal operation, the switching circuit supplies the normal operation plate line voltage to the plate line driver to apply the voltage to the plate line, when removing remanent polarization from the ferroelectric capacitor, the switching circuit supplies the remanent polarization removing plate line voltage to the plate line driver to apply the voltage to the plate line, such that an absolute value of polarization remaining in the ferroelectric capacitor is smaller than an absolute value of polarization remaining in normal operation.
In this semiconductor memory, the switching circuit can be externally given a command and selectively supply one of the normal operation plate line voltage and the remanent polarization removing plate line voltage to the plate line driver.
Alternatively, the switching circuit can comprise a first switching element having a control terminal connected to an external terminal, an input terminal to which the normal operation plate line voltage is input, and an output terminal connected to an input terminal of the plate line driver, and a second switching element having the control terminal connected to the external terminal, an input terminal to which the remanent polarization removing plate line voltage is input, and an output terminal connected to an input terminal of the plate line driver, and one of the first and second switching elements can be turned on in accordance with a signal input to the external terminal, thereby supplying one of the normal operation plate line voltage and the remanent polarization removing plate line voltage to the plate line driver.
Also, the plate line voltage generating circuit can comprise a plurality of resistors or diodes connected in series between a power terminal and a ground terminal, and a plurality of fuses connected between nodes connecting the plurality of resistors or diodes and an output terminal, and the remanent polarization removing voltage output from the output terminal can change in accordance with the presence/absence of fusing of the fuses.
Furthermore, the plate line voltage generating circuit can comprise a plurality of resistors connected in series between a power terminal and a ground terminal, a plurality of transistors each having a source and drain connected between nodes connecting the resistors and an output terminal, and a control circuit connected to a gate of each of the transistors, and the control circuit can apply a voltage to the gate of the transistor to control conduction in accordance with an externally given command, thereby changing the remanent polarization removing plate line voltage output from the output terminal.
In the semiconductor memories and their testing methods according to the present invention described above, polarization remaining in a ferroelectric capacitor is removed after testing. Consequently, it is possible to prevent the ferroelectric capacitor from causing imprint by thermal history in steps after the testing steps, thereby preventing deterioration of the characteristics and shortening of the product life.
REFERENCES:
patent: 5270967 (1993-12-01), Moazzami et al.
patent: 5889696 (1999-03-01), Kawakubo et al.
patent: 5978251 (1999-11-01), Kraus et al.
patent: 6125051 (2000-09-01), Kang
Elms Richard
Phung Anh
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