Method of fabricating a thin film transistor with metal...

Details Method of fabricating a thin film transistor with metal... Method of fabricating a thin film transistor with metal...

2000-05-12

2002-05-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S161000, C438S558000

Reexamination Certificate

active

06391691

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a thin film transistor used, for example, in liquid crystal displays and in large scale integrated circuits (hereinafter referred to as LSI) and a method of fabricating the same.
BACKGROUND OF THE INVENTION
In order to achieve a good ohmic contact between source and drain electrodes and a semiconductor layer made of, for example, amorphous silicon (hereinafter referred to as an a-Si layer) in fabricating a thin film transistor, there has been a method in which an n
+
-type a-Si layer is formed on metal layers for use in the source and drain electrodes, and an ohmic contact structure is constructed between the source and drain electrodes and the a-Si layer by etching them simultaneously using a photoetching process. However, when this method is employed, an n
+
type layer is not formed in an etched section, and a current concentration occurs at the ends of the source and drain electrodes where the n
+
-type layer is formed, resulting in a reduction in an effective contact area. Accordingly, there has been a problem that the ohmic contact is not brought about. That is, there has been a problem of a charge crowding effect.
A plasma doping method was developed to overcome such problem. In this method, phosphorus atoms (hereinafter referred to as P atoms) are diffused into the source and drain electrodes by generating PH
3
plasma on the source and drain electrodes. Thereafter, the P atoms are diffused into an a-Si film by forming the a-Si film, and an n+-type layer is formed at the interface between the source and drain electrodes and the a-Si film. However, to achieve a low contact resistivity by this method, PH
3
plasma doping for a long time must be performed. Implementation of the PH
3
plasma doping for a long time allows the P atoms to invade into a base layer (SiO
2
layer or glass substrate) between the source and drain regions, thus forming a leakage path. As a result, the turn ON/OFF current ratio of MOS transistors can not be set to be sufficiently large. The following Table 1 shows the contents of phosphorus in MoW alloy and glass which have been subjected to PH
3
plasma doping under various conditions. The contents were measured by an ESCA (electron spectroscopy for chemical analysis).
TABLE 1
P/MoW
P/glass
Ratio
Condition 1
222.11
9.72
22.85082
Condition 2
287.48
0.36
798.5556
Condition 3
194.81
4.39
44.37585
Condition 4
189.61
6.62
28.64199
Condition 5
219.92
7.35
29.92109
Condition 6
215.52
5.84
36.90411
Condition 7
217.39
7.57
28.71731
Condition 8
170.22
3.07
55.44625
Condition 9
314.57
6.58
47.80699
Condition 10
324.52
5.05
64.26139
Condition 11
266.19
8.47
31.42739
Condition 12
238.71
4.41
54.12925
Condition 13
327.26
10.83
30.21791
As understood from the Table 1, the ratios of phosphorus in the MoW alloy to the phosphorus in the glass are 800:1 at maximum. Accordingly, the conventional technology using the foregoing PH
3
plasma doping can not avoid the problem of a leakage path.
The object of the present invention is to provide a thin film transistor which is capable of achieving a good ohmic contact between respective source and drain electrodes and a semiconductor layer and solving the problems of the ON/OFF current ratio and the leakage path, and a method of fabricating the same.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method of fabricating a thin film transistor is described comprising the steps of:
forming a semiconductor oxide layer on a substrate;
forming substantially oxygen-free metal source and drain electrodes on foregoing semiconductor oxide layer;
forming a first semiconductor layer containing impurities on the foregoing semiconductor oxide layer and the foregoing source and drain electrodes, and diffusing the impurities contained in the foregoing first semiconductor layer into the foregoing semiconductor oxide layer and the foregoing source and drain electrodes;
selectively etching, by an H
2
plasma etching processing, the foregoing first semiconductor layer and a region of the foregoing semiconductor oxide layer containing the impurities;
forming a second semiconductor layer on the foregoing source and drain electrodes, and diffusing the impurities contained in the foregoing source and drain electrodes into the foregoing second semiconductor layer;
forming an insulating film for a gate dielectric on the foregoing second semiconductor layer;
forming a conductive layer for a gate electrode on the foregoing gate dielectric; and
etching the foregoing conductive layer for the gate electrode, the foregoing gate dielectric and the foregoing second semiconductor layer into a desired pattern so as to form the gate electrode, the gate dielectric and a semiconductor layer.
The invention further provides a method for fabricating a thin film transistor comprising the steps of:
forming substantially oxygen-free metal source and drain electrodes on a substrate;
forming a first semiconductor layer containing impurities on the foregoing substrate and the foregoing source and drain electrodes, and diffusing the impurities contained in the foregoing first semiconductor layer into foregoing substrate and the foregoing source and drain electrodes;
selectively etching, by an H
2
plasma etching processing, the foregoing first semiconductor layer and a region of the foregoing substrate containing the impurities;
forming a second semiconductor layer on the foregoing source and drain electrodes, and diffusing the impurities contained in the foregoing source and drain electrodes into the foregoing second semiconductor layer;
forming an insulating film for a gate dielectric on the foregoing second semiconductor layer;
forming a conductive layer for a gate electrode on the foregoing insulating film; and
etching the foregoing conductive layer for the gate electrode, the foregoing insulating film and the foregoing second semiconductor layer to a desired pattern, thereby the gate electrode, the gate dielectric and a semiconductor layer being formed.
The first semiconductor layer containing impurities, for example, phosphorus, formed on the semiconductor oxide layer and the source and drain electrodes and phosphorus-diffused portions of the foregoing semiconductor oxide layer and the foregoing substrate are selectively etched by the H
2
plasma etching processing. However, phosphorus-diffused portions of the foregoing substantially oxygen-free metal source and drain electrodes are not etched. Accordingly, the phosphorus is diffused from the foregoing source and drain electrodes into the second semiconductor layer formed thereon, thus forming an ohmic contact. On the other hand, since portions into which the phosphorus is diffused do not remain on the semiconductor oxide layer and the substrate between the source and drain electrodes, the problem of the leakage path in the above described conventional plasma doping method does not occur.
Materials for the source and drain electrodes should not be etched by the H
2
plasma etching under the condition that the phosphorus is diffused thereinto. Accordingly, it is preferable that the material for the source and drain electrodes is a substantially oxygen-free metal, particularly a MoW alloy.


REFERENCES:
patent: 4892837 (1990-01-01), Kudo
patent: 5700714 (1997-12-01), Ogihara et al.
patent: 5981317 (1999-11-01), French et al.
patent: 6251715 (2001-06-01), Jung et al.
patent: 6-22244 (1994-03-01), None

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