Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-05-22
2002-01-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000
Reexamination Certificate
active
06342409
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-18387, filed on May 20, 1999, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a stagger type polycrystalline silicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
In order to form a polycrystalline silicon layer as an active layer of a TFT, an intrinsic amorphous silicon layer is first deposited on a substrate using a plasma chemical vapor deposition (PCVD) technique or a low pressure chemical vapor deposition (LPCVD) technique so that an amorphous silicon layer is formed. Second, the amorphous silicon layer is crystallized through one of several processes that may include a laser annealing technique, a solid phase crystallization (SPC) technique, and a metal induced crystallization (MIC) technique.
FIGS. 1A
to
1
D are cross-sectional views illustrating a known process of manufacturing a stagger type Poly-Si TFT. As shown in
FIG. 1A
, source and drain electrodes
2
and
4
are formed on a substrate
1
, and source and drain regions
6
and
8
, which are ohmic contact layers with an n-type or p-type impurity, are formed on the source and drain electrodes
2
and
4
, respectively. As shown in
FIG. 1B
, an amorphous silicon layer
10
is deposited on the source and drain regions
6
and
8
while covering the exposed portions of the substrate
1
. Then, the amorphous silicon layer
10
undergoes the crystallization process using the laser annealing technique together to form a polycrystalline silicon layer together with the source and drain regions
6
and
8
. Before the crystallization process, dehydrogenation is typically performed to prevent a surface of the polycrystalline layer from being damaged due to hydrogen.
At this point in the described Poly-Si TFT fabrication process, the layers to be crystallized differ in thickness at certain locations of the amorphous silicon layer
10
. Specifically, the portion of the amorphous silicon layer
10
where the polycrystalline silicon layer is to be formed is only one layer thick, while the portion of the amorphous silicon layer
10
that overlaps the source and drain regions
6
and
8
is two layers thick. As described above, the amorphous silicon layer
10
will be crystallized simultaneously with the source and drain regions
6
and
8
. Therefore, an energy density capable of crystallizing the single layer-thick amorphous silicon layer
10
and the two layer-thick source and drain regions
6
and
8
at the same time is required. However, there is a problem in that the required energy density causes grains of the polycrystalline silicon layer
10
to be very small.
Subsequently, an activation process using a laser beam or a high-temperature, long-duration heat-treatment process is performed to activate the source and drain regions
6
and
8
. In the embodiment shown in
FIGS. 1B and 1C
, the source and drain regions
6
and
8
and the amorphous silicon layer
10
are formed from the same material. Through the crystallization process, the two separate layers depicted in
FIG. 1B
will be reduced to a single polycrystalline silicon layer
10
. Then, as shown in
FIG. 1C
, the polycrystalline silicon layer
10
is patterned into an active layer
10
′. A gate insulating layer
12
of SiO
2
or SiN
X
is formed on the active layer
10
′. As shown in
FIG. 1D
, a gate electrode
14
is formed on the gate insulating layer
12
, and the gate electrode
14
is narrower in width than the gate insulating layer
12
.
In the process of manufacturing the stagger type Poly-Si TFT described above, the active layer
10
′ may be disadvantageously severed at the step-shaped portions of the source and drain electrodes
2
and
4
. This effect occurs because the source and drain electrodes
2
and
4
expand or contract due to thermal expansion stresses caused by the laser beam or high temperature during the crystallization process. However, this effect can be avoided by using the same material for the source and drain electrodes
2
and
4
as for the polycrystalline silicon layer
10
. Specifically, in such a case the source and drain electrodes
2
and
4
have the same thermal expansion coefficient as that of the polycrystalline silicon layer and therefore the severing of the polycrystalline silicon layer at the step-shaped portions of the source and drain regions can be inhibited.
However, as described above, grains of the polycrystalline silicon layer are disadvantageously small in size.
Further, in the case of using the MIC technique for crystallization, there is a disadvantage in that the processing time is lengthy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a stagger type Poly-Si TFT having a good electric characteristics and a method of manufacturing the same with a short processing time.
In order to achieve the above object, the present invention provides a method of manufacturing a polycrystalline silicon thin film transistor, comprising; forming a buffer layer on a substrate; depositing an amorphous silicon layer with an impurity on the buffer layer and patterning the amorphous silicon layer with the impurity into source and drain regions, the source and drain regions being spaced apart from each other; forming a metal layer over the entire substrate while covering the source and drain regions; depositing an intrinsic amorphous silicon layer on the metal layer; applying a voltage to the intrinsic amorphous silicon layer to simultaneously crystallize the intrinsic amorphous silicon layer and the source and drain regions so that the intrinsic amorphous silicon layer is converted into a polycrystalline silicon layer; and patterning the polycrystalline silicon layer to form an active layer so that part of the polycrystalline silicon layer overlaps the source and drain regions.
The present invention further comprises forming a gate insulating layer and a gate electrode on the active layer; forming a passivation film over the entire substrate while covering the gate electrode; forming contact holes; and forming source and drain electrodes, contacting with the source and drain regions respectively through the contact holes.
The present invention further comprises the step of ion-doping the polycrystalline silicon layer using the gate electrode as a mask after formation of the gate electrode to form a Lightly-Doped-Drain (LDD) structure.
The gate insulating layer and the gate electrode are spaced apart from the source and drain regions, and the buffer layer, the passivation film, and the gate insulating layer are all made of a material selected from a group consisting SiNx, SiO
2
, and tetra ethoxy silane (TEOS). The amorphous silicon layer with the impurity is an n-type semiconductor containing PH
3
gas or a p-type semiconductor containing B
2
H
6
gas. The metal layer is made of a material selected from a group consisting of Ni, Pb, and Co. The metal layer can be located on the intrinsic amorphous silicon layer.
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pate
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Niebling John F.
Whitmore Stacy A
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