Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1999-11-24

2002-04-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S687000, C438S700000, C438S754000, C438S906000, C438S725000

Reexamination Certificate

active

06376364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device. More particularly, this invention relates to a method of fabricating a semiconductor device which comprises the step of forming a conductive layer made of copper or a copper alloy as a principal component.
2. Description of the Related Art
As the integration density and operational speed of LSI semiconductor devices have increased, miniaturization and multi-layered wiring structures in LSI semiconductor devices have also increased. However, the miniaturization of wiring results in increased wiring resistance and a drop in reliability. Consequently, Cu material having low resistance and a high melting point must be used in place of Al alloys that have been used in the past.
A semiconductor device fabrication method according to the prior art, that includes a Cu wiring step, is shown in FIGS.
2
(
a
) to
2
(
g
).
As shown in FIG.
2
(
a
), transistors and capacitors are fabricated by first forming device isolation regions (SiO
2
film)
1
and gate electrodes
3
on a silicon (Si) substrate
23
having diffusion layers (source/drain)
2
or the like by a conventional photolithography, a conventional dry etching and a conventional CVD method, and implanting various ions. Thereafter, a BPSG film
5
is deposited by a CVD method, and flattening is conducted by a CMP method. Contact holes
4
are bored by a photolithography and dry etching process with a photoresist
6
as a mask. Incidentally, in FIG.
2
(
a
), the surface of the gate electrodes
3
and the surface of the diffusion layers
2
are silicidized to form suicide layers
3
a
and
2
a
, respectively, in order to lower the resistance. Reference numeral
2
b
represents a low concentration diffusion layer for preventing a short-channel effect, and reference numeral
3
b
represents a side wall.
Next, as shown in FIG.
2
(
b
), a TiN/Ti laminate film
7
is deposited by a sputtering in each contact hole
4
. A tungsten (W) film
8
is then deposited by a CVD method. Then, flattening is carried out by a CMP method so that the TiN/Ti laminate film
7
and the W film
8
remains only in each contact hole and thereby W plugs are formed.
As shown in FIG.
2
(
c
), a PE-SiO
2
film
9
is deposited by a CVD method on the W plugs and BPSG film
5
, and contact holes
10
for wiring are formed on the W plugs by a photolithography and dry etching process.
As shown in FIG.
2
(
d
), a barrier metal
11
made of metal such as Ti, TiN, Ta, TaN or WN is deposited onto the W plugs by a reactive sputtering or CVD method, and a Cu film
12
is deposited further by sputtering, CVD or ECD method. Flattening is carried our by a CMP method so as to leave the barrier metal
11
and the Cu film
12
only in each contact hole for wiring, and thereby a Cu wiring in a first tier is formed.
Next, as shown in FIG.
2
(
e
), a SiN film
13
and a SiO
2
film
14
are serially deposited on the Cu wiring
12
in the first tier, and grooves
15
for wiring in a second tier are formed by a photolithography and dry etching process. Via-holes
17
are then opened with a photoresist
16
as a mask by a dry etching process using a fluorine-containing gas. The order of the two operations, i.e., the opening of the via-holes and the formation of the grooves for wiring, may be reversed. Incidentally, since Cu has a low vapor pressure, Cu reacts with the gas used for the dry etching during the formation process of the via-holes. In consequence, a copper-containing deposit
19
formed as the reaction product adheres to a side wall portion and an upper portion of the via-holes. Also, fluorine (F) used for the dry etching penetrates into the bottom of the via-holes, and the surface of the Cu wiring
12
in the first tier changes to a high resistance layer
18
(a high resistance layer comprising a mixture of Cu and F).
As shown in FIG.
2
(
f
), a subsequent resist ashing process removes the photoresist and the copper-containing deposits adhering to the side wall portion of the via-hole. The ashing conditions (in the case of a resist film thickness of 1,000 nm) at this time are as follows:
O
2
: 300 sccm,
pressure: 1 Torr,
microwave output: 1,400 W,
temperature: 200° C.,
time: 60 to 90 seconds.
In consequence, the copper-containing deposits on the via-hole side wall and the high resistance layer at the via-hole bottom are converted to F-containing Cu oxides (CuO
2
or CuO)
20
by plasma of the heated oxygen employed in the ashing process. The Cu oxides are thereafter removed by heat-treatment at 200 to 500° C. for one minute to one hour under a low pressure H
2
atmosphere. Alternatively, the surface of the Cu wiring in the first tier is oxidized beforehand, and during removal of the resist, this Cu oxide film is removed from the bottom of the via-holes by incessantly circulating a solution containing citric acid (trade name “Shumma 200K”, product of Osaka Sasaki Kagaku, Japan) heated to 60 to 90° C. As for the via-hole bottom, oxidation of Cu is reduced to a minimum by a treatment to strip off the resist using the oxygen plasma while cooling the substrate or by a treatment to strip the resist using an organic resist stripper.
Ar sputter/etching is conducted as a pre-treatment for depositing a barrier metal so as to remove an insulating layer of CuO or the like which has formed at the bottom of the via-hole. A barrier metal
21
is deposited by a sputtering or CVD method in the via-holes formed on the Cu wiring in the first tier and in the grooves for wiring in the second tier, as shown in FIG.
2
(
g
). Subsequently, a Cu film
22
is deposited by a sputtering, CVD or ECD method. Then, flattening is carried our by a CMP method so as to leave the barrier metal and the Cu film only in the via-holes and the grooves, thereby forming a Cu wiring in the second tier.
Thereafter, the process steps of FIGS.
2
(
e
) to
2
(
g
) are repeated to form multi-layered wiring using Cu as a wiring material.
When Cu is used as the wiring material of the semiconductor device as described above, Cu is exposed to the dry etching gas and to the ashing treatment for removing the resist during the fabrication process, and thereby forms fluorine-containing copper oxide. Though this oxide is removed by the heat-treatment in the H
2
atmosphere or by the treatment using the citric acid solution under the heated state, Cu is denatured by the high temperature heat-treatment, and its reliability as a wiring material drops.
When the oxide film is formed in advance on the surface of the Cu wiring in the first tier before the formation of the via-holes as described above, control of the thickness of the oxide film is difficult.
Under the related art resist ashing conditions, the deposits cannot be oxidized completely and thus cannot be removed completely with citric acid. The thickness of the resulting Cu oxide film can be decreased by the oxygen plasma treatment while the substrate is cooled, or by the organic resist stripper treatment. However, even when such a process is conducted, the Cu-containing deposits on the side wall and upper portions of the via-holes and the high resistance layer at the hole bottom cannot be removed. The insulating layer, such as CuO formed at the bottom of the via-holes, is removed by conducting Ar sputtering/etching before the formation of the barrier metal in order to obtain a low and stable resistance value in the via-holes. The treatment must be continued for a long time unless the Cu surface oxide layer is removed completely in the preceding step. When Cu remains in an inter-layer insulating film, the problem of a drop in the break down voltage of the insulating film occurs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a semiconductor device that can perfectly clean the surface of Cu wiring and can perfectly remove unnecessary deposits.
In accordance with one aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:

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