Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-05-25
2002-09-03
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S700000, C438S701000, C438S706000, C438S717000, C438S718000, C438S719000
Reexamination Certificate
active
06444540
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor apparatus, and more particularly to a method for fabricating a semiconductor apparatus having a trench region for isolating semiconductor devices in the apparatus.
BACKGROUND OF THE INVENTION
For isolating semiconductor devices in a semiconductor apparatus, trench isolation technique has been used. According to a conventional method, an SiN layer is formed on a semiconductor substrate; then trench regions are formed by etching using the SiN layer as a mask. After that, an oxide layer is provided in the trench regions by a CVD process; and then, the oxide layer is removed by a CMP process.
According to such a conventional method, sharp corners of the trench regions may be exposed when the SiN layer is removed. As a result, characteristics of semiconductor devices may be changed, and electric field is concentrated at the exposed corners of the trench regions.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor apparatus in which a trench region is fabricated to have an upper edge or upper corner which is not exposed.
Another object of the present invention is to provide a semiconductor apparatus in which a trench region is fabricated not to have sharp upper edge or upper corner.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor apparatus includes a substrate on which a plurality of semiconductor devices are formed; a mask layer formed on the substrate to have an opening which corresponds to a device isolating region; a trench region formed by etching the substrate using the mask layer as an etching mask; and an insulating layer filled in the trench region so that an upper edge or upper corner of the trench region is not exposed.
The upper edge of the trench region may be rounded-off. The mask layer may be formed so that the opening is expanded outwardly to cover the upper edge of the trench region completely.
According to a second aspect of the present invention, a method includes the steps of providing a substrate on which a plurality of semiconductor devices are formed; performing a first etching treatment to the substrate with a first etching gas comprising CF
4
to form a base trench having a rounded-off upper edge or tapered upper edge; performing a second etching treatment to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge; and forming an insulating layer on the substrate to fill up the trench region therewith.
The first etching gas may include HBr. Preferably, the ratio of flow rate of HBr and CF
4
is between 1:2 and 1:5.
The first etching gas may further include CH
2
F
2
. Preferably, the ratio of flow rate of CF
4
and CH
2
F
2
is between 2:1 and 3:1. Further, the upper edge of the trench region may be rounded off before forming the insulating layer.
According to a third aspect of the present invention, a method includes the steps of: providing a substrate on which a plurality of semiconductor devices are formed; providing a mask layer on the substrate to have an opening corresponding to a device isolating region; performing a first etching treatment to the substrate using the mask layer as an etching mask to form a trench region on the substrate; enlarging the opening of the mask layer so that an upper edge of the trench region are fully exposed; and providing an insulating layer on the substrate so that the insulating layer extends outwardly from the trench region to cover the upper edge of the trench region completely.
Preferably, the opening of the mask layer is enlarged in the range of 300 Å to 500 Å in a horizontal direction on the substrate. The opening of the mask layer may be enlarged by an isotropic etching process.
Further, a thermal oxidation treatment may be carried out to the substrate after enlarging the opening of the mask layer so that the upper edge of the trench region is rounded off.
A second etching treatment may be carried out to the substrate after the opening of the mask layer is enlarged so that the upper edge of the trench region is tapered. In this case, preferably, a thermal oxidation treatment is carried out to the substrate after the second etching treatment so that the tapered upper edge of the trench region is rounded off.
The upper edge of the trench region may be rounded off before enlarging the opening of the mask layer.
REFERENCES:
patent: 5994229 (1999-11-01), Chen et al.
patent: 6180533 (2001-01-01), Jain et al.
patent: 6218309 (2001-04-01), Miller et al.
Kawada Shinzi
Kawano Hiroyuki
Oki Electric Industry Co,. LTD
Talbott David L.
Volentine & Francos, PLLC
Zarneke David A
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