Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-14
2002-07-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06415416
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a database for use in the design of an integrated circuit device and to a design method using such a database, and more particularly relates to design technology to cope with system-on-chip implementation.
A semiconductor device for an electronic unit has been fabricated until just recently by forming individual types of LSI's such as memories and processors on respective semiconductor chips and then mounting these chips on a motherboard like a printed wiring board.
Over the past few years, however, a semiconductor device is increasingly required to reduce the overall size, weight, power dissipation and fabrication cost thereof to further broaden the industrial applicability of an electronic unit including such a device. Among other things, a consumer electronic unit for use in digital information processing has to meet all of these requirements more often than any other electronic unit. Responsive to such a demand from the electronic unit industry, the prime target of semiconductor technology is going to shift from memories to system LSI's.
Specifically, a system LSI is a single-chip implementation including memories and various types of logic circuits on a single chip. To form a system LSI, not only the technology of forming devices like transistors with dissimilar structures on a common substrate, but also the design technology thereof should be greatly innovated.
Thus, according to a suggested technique of designing a system LSI, a database is prepared in advance to design an arbitrary block consisting of a great number of cells, each implementing a required function, e.g., a so-called “functional block”. By using such a database, any desired system LSI can be designed as a combination of blocks.
FIG. 8
is a block diagram schematically illustrating an arrangement of a conventional system LSI. As shown in
FIG. 8
, the system LSI includes four blocks
11
A,
11
B,
11
C and
11
. The blocks
11
A and
11
B are first and second universal asynchronous receiver-transmitter (UART
1
and
2
) blocks, the block
11
C is a direct memory access (DMA) block and the block
11
D is a timer (TIM) block. Each of these blocks
11
A through
11
D includes: an internal controller (labeled as “Control Logic”)
12
A,
12
B,
12
C or
12
D; an interface circuit (“Host I/F”)
13
A,
13
B,
13
C or
13
D; an FIFO memory (“TX-FIFO”)
14
A,
14
B,
14
C or
14
D; and a clock generator (“CLKGEN”)
15
A,
15
B,
15
C or
15
D. All of these block components are provided as individual cells. The system LSI actually includes a great number of blocks other than those illustrated in
FIG. 8
, but only these four blocks
11
A through
11
D are illustrated in FIG.
8
for sake of simplicity.
According to the conventional design method, a specific physical structure for performing an intended function has been defined in advance for each block. Thus, in the physical design of an overall semiconductor device, only the interconnections among the blocks and peripheral circuitry have to be newly designed. In this manner, the conventional method tries to increase the design efficiency considerably.
The conventional design technique, however, has the following drawbacks. In the structure shown in
FIG. 8
, the FIFO memories
14
A through
14
D and clock generators
15
A through
15
D are provided for the respective blocks
11
A through
11
D. However, at least one of the FIFO memories
14
A through
14
D might be shared at least between a pair of blocks
11
A,
11
B,
11
C,
11
D. Also, a common clock signal might be applicable to all of these blocks
11
A through
11
D. Even so, the data defined for these blocks still should be used as it is and none of the FIFO memories
14
A through
14
D and clock generators
15
A through
15
D is omissible according to such a design method. As a result, power is dissipated in vain, structure is unnecessarily complicated and occupied area increases for nothing in such a situation.
SUMMARY OF THE INVENTION
The present inventors noticed that the root of the problems involved with the conventional block-based design method lies in that the design of a semiconductor device as a system LSI is not managed at a higher level but at a lower functional design level. An object of the present invention is providing a semiconductor device optimized to meet various requirements imposed by the electronic industry, like downsizing and reduced power dissipation, by designing the overall device at the higher specification, architectural and RT levels, while still using the design data for respective blocks.
A first exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including a plurality of blocks. The method includes the steps of: a) defining exclusive operation information among the blocks; b) defining interconnection information about a sharable resource within each said block; and c) extracting a resource sharable among the blocks based on the information about the sharable resource and the exclusive operation information among the blocks.
According to the first method, a sharable resource can be extracted easily. Thus, physical resources required can be cut down by taking advantage of the sharable resource.
In one embodiment of the present invention, the first method preferably further includes the step of d) generating interconnection information about the resource sharable among the blocks after the step c) has been performed. In such an embodiment, a semiconductor integrated circuit can be designed by using the sharable resource smoothly.
In this particular embodiment, the first method may further include the step of defining timing information about the sharable resource within each said block before the step d) is performed. In the step d), the timing information is used. In such an embodiment, more accurate interconnection information can be generated about the shared resource.
In an alternate embodiment, the first method may further include the step of e) generating interconnection information about an optimized top-level hierarchy based on the interconnection information about the resource sharable among the blocks and interconnection information about a top-level hierarchy that has been generated in advance. In such an embodiment, the overall system performance of a semiconductor integrated circuit device can be estimated more accurately. Thus, an optimum database can be selected for each block.
In another alternate embodiment, the first method may further include, before the step d) is performed, the steps of: defining a standard interface for the sharable resource; and generating information about the standard interface for the sharable resource. In the step d), the standard interface information is used. In such an embodiment, more accurate interconnection information can be generated.
A second exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including: a plurality of blocks, each consisting of a plurality of cells; and a resource shared among the blocks. The method includes the steps of: a) defining exclusive operation information among the blocks; and b) generating a signal switching control for the resource shared among the blocks based on the exclusive operation information.
According to the second method, data can be generated using the exclusive operation information such that the shared resource can be taken advantage of smoothly among the respective blocks without mutual interaction.
In one embodiment of the present invention, the second method preferably further includes the step c) of defining interconnection information about a top-level hierarchy and then generating interconnection information about an optimized top-level hierarchy after the step b) has been performed. In such an embodiment, the overall system performance of a semiconductor integrated circuit device can be estimated more accurately. Thus, an optimum database can be selected for each block.
Fujiwara Makoto
Motohara Akira
Yokoyama Toshiyuki
Do Thuan
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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