Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2000-07-10
2002-05-07
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S733000, C714S030000
Reexamination Certificate
active
06385755
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing system and a logic LSI to which a master/checker method is applied, with the objective of improving the fault detection efficiency.
2. Description of Related Art
An information processing apparatus to which a master/checker method is applied, with the objective of improving the fault detection efficiency, already has been presented. For example, an information processing apparatus having the above-mentioned feature is disclosed in “Fault Tolerance Achieved in VLSI”, by R. Emmerson et al., IEEE Micro., December 1984, pp 34-43.
In the above-mentioned apparatus, data output from a master unit is input to a checker unit via a data bus. The output data of the master unit input to the checker unit is compared with corresponding output data of the checker unit by a comparator provided in the checker unit. If a result of the comparison indicates a disagreement between both data, the comparator outputs a fault detecting signal, and the operation of the information processing apparatus is stopped.
On the other hand, due to recent rapid innovation in LSI processing techniques, a processor including many peripheral circuits, such as cache memory, has been developed. Therefore, it has been considered not sufficient for fault detection in an apparatus containing a plurality of processors, such as mentioned above, to be carried out merely by comparing a pair of data transmitted to a data bus.
As a method of improving the fault detection efficiency, it also has been proposed to execute a comparison between data output from one of the peripheral circuits integrated in a processor provided in a master unit and data output from a corresponding one of the peripheral circuits integrated in a processor provided with a checker, in addition to the comparison between data output on the data bus. However, if the fault detection is carried out for output data of all integrated circuits in a master unit and a checker, a new problem is caused, that is, a comparator for comparing data processed in the integrated circuits and the wiring among the integrated circuits and the comparators need a large area, respectively.
As a method of resolving the above-mentioned problem, “A fault detection processing method” is disclosed in JP-A-129426/1985 by Hujiwara et al. In this method, the fault detection is realized by executing a comparison between a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a master unit and a result of an exclusive OR calculation for data output from the integrated circuits of a processor in a checker. Although this method avoids the need to increase the area needed for a comparator and the wiring, faults of 2 bits cannot detected. Therefore, by this method, a sufficient fault detection efficiency can not be attained.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide an information processing system and a logic LSI to which a master/checker method is applied, with the result of improving the fault detection efficiency, while suppressing the need to increase the amount of wiring (between pins of two LSIs in a system wherein a master unit and a checker are composed by using two different LSIs, or between a master unit and a checker in a system wherein a master unit and a checker are integrated in one LSI), and to increase the area needed for a comparator executing the comparison between a pair of corresponding data output from the master unit and the checker.
The first way to attain the above-mentioned objective is to provide an information processing system, including a plurality of information processing units, in which a fault occurring in the plurality of information processing units is detected by carrying out a comparison among data, each of the data being processed and output by each of the plurality of information processing units,
wherein each of the plurality of information processing units includes a processor circuit in which a plurality of internal circuits is integrated, an internal processing result outputting means for outputting respective result data processed by respective ones of the plurality of internal circuits, and an internal data selection circuit for selecting and outputting a selected one of the result data output from the internal processing result outputting means, at every predetermined timing, and
the information processing system further includes a comparator for executing a comparison among corresponding data, each of which is selected and output from the internal data selection circuit of each information processing unit, and for outputting a result of the comparison.
In this information processing system, it is preferable that buses are used for connection between the information processing units, and between the comparator and each of the information processing units, and at least one of the information processing units inputs data output from the internal data selection circuit provided in the unit itself to the comparator via the buses.
Further, in this information processing system, it is possible for the at least one of the information processing units, inputting data output from the internal data selection circuit provided in the unit to the comparator via the buses, to further include a first selector for selecting either the result data output from the processor circuit provided in the unit or data output from the internal data selection circuit provided in the unit.
The information processing system according to the present invention further includes a memory device, and data which is output from the above-mentioned processor unit to the memory device via the buses is also input to the comparator and compared with data which is output from the processor circuits of other information processing units and input to the comparator.
Further, in this information processing system, it is possible to include the comparator in one of the information processing units, and the information processing unit including the comparator further is provided with a second selector for selecting and outputting either data output from the processor circuit provided in the unit or data output from the internal data selection circuit provided in the unit, in synchronism with data selection by the first selector included in another information processing unit.
In the following, an example of operations of the information processing system according to the present invention will be explained.
The internal processing result outputting means of each processor circuit outputs result data processed by each of the internal circuits. The internal data selection circuit selects and outputs one of the result data output from the internal processing result data outputting means, at every predetermined timing (for example, an execution machine cycle of the processor circuit). The comparator executes a comparison between the data input from the internal data selection circuits provided in two of the information processing units, and outputs a result of the comparison. By monitoring the result of the comparison, it is possible to detect a fault occurring in the information processing system. That is, if the two compared data do not agree with each other, it means that some fault is occurring in the information processing system.
If the data output from the internal data selection circuit of each information processing unit is input to the comparator via the above-mentioned buses, it is not necessary to provide exclusive wires for inputting and outputting the data input to the comparator. Further, by selecting and outputting either the data output from the processor circuit or the data output from the internal data selection circuit to the buses, via the first selector, wires and terminals connected to the buses can be commonly used.
Moreover, if the comparison is carried out for data output from the processor circuit to the memory device by using the comparator, a fault occurrence can be also dete
Hotta Takashi
Kanekawa Nobuyasu
Murabayashi Fumio
Shimamura Kotaro
Shimomura Tetsuya
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tu Christine T.
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