Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

2000-08-22

2002-03-26

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S065000, C365S149000, C365S185110, C365S230030, C365S230060

Reexamination Certificate

active

06363003

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating a ferroelectric material (hereinafter referred to as a “ferroelectric memory device”). More specifically, the present invention relates to a ferroelectric memory device including memory elements (memory cells) each composed of at least one semiconductor transistor and at least one ferroelectric capacitor, such that at least one of the memory cells is selected based on activation of the semiconductor transistor associated therewith, and information is stored in the selected memory cell based on a polarization direction of the associated ferroelectric capacitor.
2. Description of the Related Art
FIGS. 9 and 10
show the respective memory cell structures of commonly-used ferroelectric memory devices
900
and
1000
. The conventional ferroelectric memory device
900
shown in
FIG. 9
is of a type referred to as “2-transistor-2-capacitor” (hereinafter “2T2C”), in which each memory cell is composed essentially of two semiconductor transistors
1
and two ferroelectric capacitors
2
. One piece of data is stored in one memory cell. The conventional ferroelectric memory device
1000
shown in
FIG. 10
is of a type referred to as “1-transistor-1-capacitor” (hereinafter “1T1C”), in which each memory cell is composed essentially of one semiconductor transistor
1
and one ferroelectric capacitor
2
. One piece of data is stored in one memory cell.
In the conventional ferroelectric memory device
900
shown in
FIG. 9
, word lines (WL
0
, WL
1
) and bit lines (BIT
0
, BIT
0
#, BIT
1
, BIT
1
#, BIT
2
, BIT
2
#, BIT
3
, BIT
3
#, etc.) intersect each other (illustrated as perpendicularly intersecting each other in FIG.
9
), and the word lines and plate lines (PL
0
, PL
1
) are disposed in parallel to each other. A source of each semiconductor transistor
1
is coupled to one of the bit lines; a drain of each semiconductor transistor
1
is coupled to a first electrode of the associated ferroelectric capacitor
2
; a gate of each semiconductor transistor
1
is coupled to one of the word lines; and a second electrode of the associated ferroelectric capacitor
2
is coupled to one of the plate lines. Furthermore, a pair of bit lines (BIT
0
and BIT
0
#; BIT
1
and BIT
1
#; BIT
2
and BIT
2
#; BIT
3
and BIT
3
#, etc.) are coupled in common to a sense amplifier
3
.
In the ferroelectric memory device
900
of
FIG. 9
, each semiconductor transistor
1
and its associated ferroelectric capacitor
2
are provided in the vicinity of an intersection between a bit line and a word line. On the other hand, in the ferroelectric memory device
1000
of
FIG. 10
, each semiconductor transistor
1
and its associated ferroelectric capacitor
2
are provided in the vicinity of an intersection between every other bit line and a word line (e.g., an intersection between the bit lines BIT
0
and BIT
0
# and the word line WL
0
).
In the ferroelectric memory devices
900
and
1000
, a memory cell may be selected in the following manner. First, the word line WL
0
may be selected so as to go high (“H”), and then a pulse voltage may be applied to the plate line PL
0
. (Similarly, the word line WL
1
may be selected so as to go high (“H”), and then a pulse voltage may be applied to the plate line PP
1
). The applied pulse voltage, if applied in the same direction as the polarization direction of each ferroelectric capacitor
2
, destroys the polarization of that ferroelectric capacitor
2
so that its polarization direction is inverted. As a result, those memory cells in which the polarization of the ferroelectric capacitors
2
is inverted output a different charge amount on the associated bit line from the charge amount output by those memory cells in which the polarization of the ferroelectric capacitors
2
is not inverted. Specifically, those memory cells in which the polarization of the ferroelectric capacitors
2
is inverted output a higher charge amount from their respective ferroelectric capacitors
2
than those memory cells in which the polarization of the ferroelectric capacitors
2
is not inverted. These differential charge amounts are amplified by the sense amplifiers
3
, resulting in “H” or “L” data being output on the corresponding bit lines.
However, in accordance with the structures of
FIGS. 9 and 10
, a large number of ferroelectric capacitors
2
are directly coupled to each plate line. Since the ferroelectric capacitors
2
have a relatively large capacitance, delays on the plate line become more problematic as more ferroelectric capacitors
2
are coupled to the plate line. In general, a ferroelectric capacitor has a capacitance which is about 10 times or more of the gate capacitance of a semiconductor transistor. Therefore, if the number of semiconductor transistors coupled to a word line is the same as the number of ferroelectric capacitors coupled to a plate line, then the plate line has a capacitance which is about 10 times or more of that of the word line.
In order to solve this problem, Japanese Laid-Open Publication No. 10-162589 proposes a “2T2C” type ferroelectric memory device
1100
structure as shown in FIG.
11
. The ferroelectric memory device
1100
includes a plurality of plate lines corresponding to each word line (so that plate lines PL
0
A and PL
0
B correspond to a word line WL
0
; plate lines PL
1
A and PL
1
B correspond to a word line WL
1
). For example, the plate lines PL
0
A and PL
0
B correspond to the word line WL
0
. The plate line PL
0
A corresponds to bit lines BIT
0
, BIT
0
#, BIT
1
and BIT
1
#. The plate line PL
0
B corresponds to bit lines BIT
2
, BIT
2
#, BIT
3
and BIT
3
#. Otherwise, the ferroelectric memory device
1100
has the same structure as that of the ferroelectric memory device
900
of FIG.
9
. Since the structure of the ferroelectric memory device
1100
reduces the number of ferroelectric capacitors coupled to the plate lines to a half of what it would be otherwise, the operational speed of the plate lines is improved.
Although not disclosed in the 10-162589 application, an application of this technique to a “1T1C” type configuration should be as shown in FIG.
12
. Specifically, plate lines PL
0
A and PL
0
B are provided so as to correspond to a word line WL
0
, and plate lines PL
1
A and PL
1
B are provided so as to correspond to a word line WL
1
. The plate lines PL
0
A and PL
1
A correspond to bit lines BIT
0
, BIT
0
#, BIT
1
and BIT
1
#. The plate lines PL
0
B and PL
1
B correspond to bit lines BIT
2
, BIT
2
#, BIT
3
and BIT
3
#. Otherwise, the ferroelectric memory device
1200
has the same structure as that of the ferroelectric memory device
1000
of FIG.
10
.
However, in accordance with the ferroelectric memory device 1100 (or 1200) shown in FIG. 11 (or 12) of the 10-162589 application, a word line is selected based on a ROW address, and a plate line is selected based on a COL address. According to this method, the sense amplifiers cannot operate before it is determined which one of the plate lines is to be activated. Under a DRAM type input (i.e., address multiplex) scheme, this results in an increased access time. Since a period of time must be waited in order for a COL address to be input, this structure cannot provide for an enhanced operational speed, in spite of the reduction of the plate line capacitance (which would otherwise enable some enhancement in the operational speed).
Furthermore, there is also a problem in that adjoining bit lines are simultaneously sensed in all of the ferroelectric memory devices
900
,
1000
,
1100
, and
1200
shown in
FIGS. 9
,
10
,
11
and
12
, thereby resulting in a reduced sensing margin (since the sensing of one bit line may always be influenced by, or subjected to the interference of, an adjoining bit line).
SUMMARY OF THE INVENTION
A ferroelectric memory device including: a matrix of memory cells each including a semiconductor transistor and a ferroelectric capacitor; a pluralit

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