Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-10
2002-07-02
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S336000, C257S408000
Reexamination Certificate
active
06414353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (semiconductor on insulator) MOSFET (metal oxide semiconductor field-effect transistor).
2. Description of the Background Art
FIG. 27
is a front sectional view of a conventional semiconductor device
151
forming the background of the present invention. In this semiconductor device
151
, an insulator film
82
is formed on a semiconductor substrate
81
, and an SOI layer
83
containing silicon as base material is formed on the insulator film
82
. Namely, the semiconductor device
151
is formed as an SOI semiconductor device.
As shown in
FIG. 27
, an n-channel MOSFET is provided in the semiconductor device
151
. An n-conductivity type source region
84
, a p-conductivity type body region
86
and an n-conductivity type drain region
85
are provided in the SOI layer
83
. The body region
86
is formed to be held between the source region
84
and the drain region
85
. The source/drain regions
84
and
85
include n
−
-conductivity type low-concentration regions
88
and
89
and n
+
-conductivity type high-concentration regions
87
and
90
respectively.
A gate electrode
93
is opposed to the body region
86
through a gate insulator film
97
. Side walls
94
are formed on side surfaces of the gate electrode
93
and the gate insulator film
97
. A source electrode supplying a source potential Vs is connected to the source region
84
, and a drain electrode supplying a drain potential Vd is connected to the drain region
85
.
As shown in
FIG. 27
, a depletion layer
92
is formed in the body region
86
along p-n junctions. However, the SOI layer
83
is formed so sufficiently thick that the depletion layer
92
does not occupy the overall body region
86
but leaves a p-type semiconductor region
91
containing holes serving as carriers in a lower portion of the body region
86
.
In other words, the SOI-type MOSFET provided on the semiconductor device
151
is formed as a MOSFET operating in a partially depleted mode (hereinafter referred to as a PD mode). The MOSFET operating in the PD mode has characteristics substantially equivalent to those of a bulk MOSFET since the depletion layer
92
does not reach the insulator film
82
.
FIG. 28
illustrates a well-known semiconductor device
152
comprising a bulk MOSFET. This semiconductor device
152
comprises not a multilayer substrate including a semiconductor substrate
81
, an insulator film
82
and an SOI layer
83
, but a single semiconductor substrate
95
. Source/drain regions
84
and
85
and a body region
86
are selectively formed in an upper portion of the semiconductor substrate
95
.
As shown in
FIG. 28
, a wide p-type semiconductor region
96
containing holes is present under a depletion layer
92
in the bulk MOSFET. The bulk MOSFET is common in this point with the MOSFET operating in the PD mode, and hence the characteristics of the former are approximate to those of the latter.
In still another conventional semiconductor device
153
shown in
FIG. 29
, on the other hand, the thickness of an SOI layer
83
is by far smaller than that in the semiconductor device
151
shown in FIG.
27
. In a MOSFET provided on the semiconductor device
153
, therefore, a depletion layer
92
reaches an insulator film
82
. In other words, the SOI-type MOSFET provided on the semiconductor device
153
is formed as a MOSFET operating in a fully depleted mode (hereinafter referred to as an FD mode).
The MOSFET (hereinafter also referred to as the MOSFET of the FD mode) operating in the FD mode advantageously obtains an ideal S factor dissimilarly to the MOSFET (hereinafter also referred to as the MOSFET of the PD mode) operating in the PD mode. The S factor, which is also referred to as a subthreshold coefficient, is defined as a slope S of a leading edge in a transition curve showing the relation between the logarithm of a main current Id and a gate potential Vg, as shown in FIG.
30
. The transition curve more sharply rises as the S factor reduces, to provide desirable switching characteristics.
In the MOSFET of the FD mode, however, electrical resistance of the source/drain regions
84
and
85
is high due to the small thickness of the SOI layer
83
, leading to inferior substantial characteristics as compared with the bulk MOSFET. In a step of forming contact holes for connecting main electrodes to the source/drain regions
84
and
85
, the contact holes disadvantageously readily reach the insulator film
82
through the SOI layer
83
due to the small thickness thereof. In other words, it is difficult to connect the main electrodes to the source/drain regions
84
and
85
.
When silicide layers are formed on surfaces of the source/drain regions
84
and
85
for reducing contact resistance between the source/drain regions
84
and
85
and the main electrodes, the silicide layers disadvantageously readily reach the insulator film
82
due to the small thickness of the SOI layer
83
. The silicide layers are easy to separate when reaching the insulator film
82
, as a matter of course.
On the other hand, the MOSFET of the PD mode having the thick SOI layer
83
causes no such problems of the MOSFET of the FD mode. However, the MOSFET of the PD mode cannot attain a small S factor advantageously obtained in the MOSFET of the FD mode. In the MOSFET of the PD mode, further, the p-type semiconductor region
91
located immediately under the depletion layer
92
is in a floating state to form an electrostatic capacitance between the p-type semiconductor region
91
and the gate electrode
93
. Consequently, a gate threshold voltage disadvantageously fluctuates.
In addition, the p-type semiconductor region
91
stores holes and hence a parasitically formed npn bipolar transistor disadvantageously readily conducts. A leakage current increases following such conduction of the parasitic bipolar transistor.
SUMMARY OF THE INVENTION
A semiconductor device according to a first aspect of the present invention is provided with circuit elements in a semiconductor chip having an SOI layer, and comprises a MOSFET and a power supply part as the circuit elements. The MOSFET comprises a source region and a drain region selectively formed in the SOI layer and a body region held between the source region and the drain region, the thickness of the SOI layer is set at a value not fully depleting the body region under a floating condition and a condition supplied with the same potential as the source region, and the power supply part generates a voltage of a constant level and supplies the voltage between the source region and the body region in a direction for enlarging a depletion layer formed in the body region.
In the semiconductor device according to the first aspect of the present invention, the SOI layer is formed in a large thickness equivalently to the conventional MOSFET operating in the PD mode, whereby the resistance of the source drain and the drain region is suppressed low. Further, contact holes for connecting a main electrode to the source region and the drain region are easy to form. In addition, a semiconductor metal compound layer can be stably formed on surfaces of the source region and the drain region. Further, it is possible to drive the semiconductor device while applying a substrate bias without floating the body region or equalizing the potential thereof to that of the source region. Thus, the present invention relaxes or solves the problems of an instable gate threshold voltage and a large leakage current.
Further, no voltage for applying the substrate bias needs to be externally supplied, whereby no terminal needs to be provided for relaying the voltage for applying the substrate bias. In addition, wires in the semiconductor device can be reduced in length. Further, no specific power source needs to be prepared for using the semiconductor device, whereby the semiconductor device is convenient to use.
A semiconductor device according to a second aspect of the present inven
Maeda Shigenobu
Maegawa Shigeto
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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