Semiconductor memory device operating in synchronization...

Details Semiconductor memory device operating in synchronization... Semiconductor memory device operating in synchronization...

1999-09-13

2002-07-30

Lane, Jack A. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S167000, C365S233100, C365S194000

Reexamination Certificate

active

06427197

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a general semiconductor memory device, and particularly to a semiconductor memory device that operates in synchronization with a clock signal.
In recent years, as CPUs have become faster, the demand has arisen for semiconductor memory devices such as the DRAM (dynamic random access memory) wherein data signals are input and output at higher signal frequencies, making them capable of sustaining faster data transfer rates.
Examples of semiconductor memory devices responsive to this demand are the SDRAM (synchronous dynamic random access memory) and FCRAM (fast cycle random access memory) which achieve high-speed operations by operating in synchronization with an externally supplied clock signal.
2. Description of the Related Art
Conventional semiconductor memory devices are now described. These descriptions relate to the operations of FCRAMs and DDR-SDRAMs (double data rate synchronous random access memories) which achieve higher speeds by performing data I/O in synchronization with the rising and falling edges of the clock signal.
In
FIG. 1
is diagrammed one example configuration for the memory-cell peripheral circuitry of a DDR-SDRAM and an FCRAM. The circuit diagrammed in
FIG. 1
comprises a capacitor
201
, NMOS transistors
202
to
212
,
223
, and
224
, and PMOS transistors
213
,
221
, and
222
. The PMOS transistors
221
and
222
and the NMOS transistors
223
and
224
configure a sense amp
220
. In the capacitor
201
, which is a memory cell, 1 bit of data is stored.
FIG. 2
is a timing chart representing a data read operation in a DDR-SDRAM having the memory-cell peripheral circuitry diagrammed in FIG.
1
. Data read timing control is now described with reference to FIG.
1
and FIG.
2
.
When data are being read out, a sequence of commands is input to the SDRAM, namely a precharge command PRE for precharging the bit lines BL and /BL to a prescribed voltage, a /RAS command (corresponding to the active command ACTV in
FIG. 2
) for row access, and a /CAS command (corresponding to the read command READ in
FIG. 2
) for column access. The /RAS command selects one row-system memory cell block from the core circuitry in the SDRAM, that is, a specific word line. The /CAS command selects a specific column from the selected word line, that is, a sense amp
220
. The core circuitry is such that the memory cells
201
are deployed in an array structure as respecting the row and column directions, with a sense amp
220
provided for each column. Accordingly, memory cell data corresponding to the selected word line are fetched to the sense amps
220
.
When an active command ACTV that is a control signal corresponding to the /RAS signal is input, the signal RASZ, which is an internal RAS signal, is generated (i.e. goes high). The signal RASZ is a signal for activating the memory core.
The signal RASZ, moreover, is a signal that causes the level of the word lines to rise, as the memory core is activated, and then activates the sense amps. For that reason, when the active command ACTV is input, in the memory core, the levels of the word lines rise in response to the signal RASZ, and the sense amp is activated. In
FIG. 1
a shared sense amp is represented. When an address is input to select a word line SW, from the precharge state wherein the bit line transfer signals BLT
0
and BLT
1
are high, the one bit line transfer signal BLT
0
will go low, and the bit lines BL and /BL in the block on the opposite side will be cut off from the sense amp
220
. Meanwhile, the other bit line transfer signal BLT
1
will stay high, the transistors
203
and
204
will continue to conduct, and the bit lines BL and /BL on the right side will remain connected to the sense amp. At the same time, the precharge signal PR becomes low, and the reset states of the bit lines BL and /BL are released. When in this status the sub-word line SW is selected, the NMOS transistor
202
functioning as a cell gate conducts, and data in the capacitor
201
are read on the bit line BL (corresponding to BL-
0
,
1
in FIG.
2
).
Next, sense amp drive signals SA
1
and SA
2
(corresponding to SA in
FIG. 2
) for driving the sense amps
220
become active (going low and high, respectively), and both the NMOS transistor
212
and PMOS transistor
213
conduct. In this state, the data on the bit lines BL and /BL are read into the sense amps
220
via the NMOS transistors
203
and
204
. The sense amps
220
thus drives the bit lines BL, /BL so that the data on the bit lines BL and /BL are amplified. Thereupon, data in all memory cells corresponding to selected word line are fetched to the sense amps throughout the whole SDRAM.
Next, when a read command READ that is a control signal corresponding to the /CAS command is input, the column line selection signal CL becomes high with suitable timing in the SDRAM, and a specific column is selected. Thereupon, the NMOS transistors
210
and
211
that are the selected column gates conduct, and the amplified data on the bit lines BL and /BL are read on global data busses GDB and /GDB (corresponding to GDB-
0
,
1
in FIG.
2
). Thereupon, the parallel data read on data busses DB and /DB (not shown in
FIG. 1
) (corresponding to DB-
0
,
1
in
FIG. 2
) via read buffers are converted to serial data and output as data DQ.
After that, when the precharge command PRE is input, the precharge signal PR goes high, the NMOS transistors
207
,
208
, and
209
conduct, and the bit lines BL and /BL are precharged to a prescribed voltage VPR. Thus, with a conventional SDRAM, the bit lines BL and /BL can be reset in preparation for the next control signal (data write or data read).
With a conventional SDRAM, therefore, the cycle from the input of the first control signal (data read) until it becomes possible to input the next control signal (data write or data read) requires 8 clocks, as indicated in the data read operation diagrammed in FIG.
2
.
FIG. 3
is a timing chart representing a data write operation in a DDR-SDRAM having the memory-cell peripheral circuitry diagrammed in
FIG. 1
, as described earlier. The timing control for this data write operation is now described with reference to FIG.
1
and FIG.
3
.
When the active command ACTV is input, as in the data read operation described above, a signal RASZ (high) that is an internal RAS signal is generated, and, internally, the memory core is activated, the levels of the word lines rise, and the sense amps are activated. When the memory core is activated, the NMOS transistor
202
conducts, and the data in the capacitor
201
are read on the bit line BL (corresponding to BL-
0
,
1
in FIG.
3
). The operation of the peripheral circuitry diagrammed in
FIG. 1
was described earlier and so is not repeated further here.
Next, the sense amp drive signals SA
1
and SA
2
(corresponding to SA in
FIG. 3
) for driving the sense amps
220
become active (going low and high, respectively), and both the NMOS transistor
212
and the PMOS transistor
213
conduct. In this state, the data on the bit lines BL and /BL are provided to the sense amps
220
via the NMOS transistors
203
and
204
. By driving the sense amps
220
, the data on the bit lines BL and /BL are amplified.
Next, when a write command WRITE is input, the serial data simultaneously input from the outside as the data signal DQ are converted to parallel data and output on data busses DB and /DB (corresponding to DB-
0
,
1
in FIG.
3
). Thereupon, the parallel data output on the global data busses GDB and /GDB (corresponding to GDB-
0
,
1
in
FIG. 3
) via write buffers are written to the sense amps
220
with the timing wherewith the column line selection signal CL represented in
FIG. 1
goes high, and those data are furthermore stored in the capacitor
201
via the bit line BL.
After that, when the precharge command PRE is input, the precharge signal PR goes high with suitable timing, the NMOS transistors
207
,
208
, and
209
conduct, and the bit lines BL and /BL are precharged to a p

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