Method of forming inter-metal interconnection

Details Method of forming inter-metal interconnection Method of forming inter-metal interconnection

1998-11-24

2002-03-05

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S725000

Reexamination Certificate

active

06352918

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the fabrication of damascene, and more particularly to a method of forming inter-metal dielectric (IMD) using a material with low dielectric constant (k).
2. Description of the Related Art
A previous method used to form metal interconnections comprises steps of depositing a metal layer on a substrate, defining the metal layer to form an interconnection layer and forming a dielectric layer on the interconnecting layer. The metal layer reflects light during a photolithography and etching process so that the method easily causes error while defining the metal layer. Furthermore, etching the metal layer is more difficult than etching the dielectric layer because of the characteristics of the metal layer.
According to the disadvantage of the previous method, a damascene process is provided. The damascene process comprises steps of forming a dielectric layer on a substrate, forming a trench in the dielectric layer and filling a metal plug in the trench.
FIGS. 1A
to
1
C are cross-sectional views showing a conventional damascene process.
In
FIG. 1A
, a substrate
100
with a planar top surface is provided. The substrate
100
comprises some devices or structures formed thereon, but not shown in the figure. A dielectric layer
102
is formed on the substrate
100
. In the dielectric layer
102
, a metal plug
103
is formed to connect to the substrate
100
.
An IMD layer
104
is formed on the dielectric layer
102
. A defined photoresist layer
106
is provided on the IMD layer
104
. According to the defined photoresist layer
106
, a part of the IMD layer
104
is removed to form a trench
107
in the IMD layer
104
a
and to expose the metal trench
103
as shown in FIG.
1
B. After removing the photoresist layer
106
, metal
108
is filled into the trench
107
to form the structure shown in FIG.
1
C.
In the damascene process, spin-on organic polymers with a low dielectric constant, such as Flare, SILK and PAE-II, are usually used to reduce interconnection parasitic capacitance, to reduce the RC delay and to mitigate cross talk between metal layers, hence, the operation speed is improved. Therefore, the low k dielectric layer is a very popular IMD material used in a high-speed integrated circuit (IC).
Similar to the material contained in photoresist layers, the material contained in the organic polymers used as IMD layers has a large proportion of carbon. The IMD layers are removed while removing the photoresist layers because of bad selectivity of the IMD layers and of the photoresist layer. That result reduces the efficiency of the photoresist layers.
An oxide layer, which is formed by plasma-enhanced chemical vapor deposition (PECVD), is usually formed on an IMD layer as a protecting layer. The PE-oxide layer is used as a hard mask to protect the IMD layer from being removed during an etching process. However, using the PE-oxide layer causes some disadvantages. For example, a plasma containing oxygen used to form the PE-oxide layer destroys the surface of the IMD layer during oxide layer formation. The destruction degrades the characteristics of the low-k IMD layer. The destruction also makes the oxide layer have a bad adhesion to the IMD layer. When the IMD layer is etched to form a trench therein or a planarization process is performed, the oxide layer may peel due to the bad adhesion. The protecting efficiency of the oxide layer is thus decreased. The peeling oxide layer causes contamination.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved method of forming an inter-metal interconnection to protect the IMD layer from being destroyed during PE-oxide layer formation. The method further prevents the low k IMD layer from being degraded and avoids the IMD layer peeling due to bad adhesion.
The invention achieves the above-identified objects by providing a method of forming an inter-metal interconnection. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal trench in the dielectric layer. The trench is filled with metal to electrically connect to the metal plug.


REFERENCES:
patent: 4519872 (1985-05-01), Anderson, Jr. et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6191028 (2001-02-01), Huang et al.
S. Wolf, “Silicon Preocessing for the VLSI Era”, Lattice Press, vol. 2, pp. 229-235, 1990.

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