Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-12-23
2002-01-08
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C711S156000, C711S168000, C711S151000, C711S158000, C710S039000, C710S052000, C710S112000
Reexamination Certificate
active
06338125
ABSTRACT:
TECHNICAL FIELD
This invention relates to a system for processing many memory requests simultaneously and in particular, a method and apparatus that receives many memory requests and tracks each request while providing a response as quickly as possible.
BACKGROUND OF THE INVENTION
Microprocessors have increased in clock speed in recent years. Only a few years ago, clock speeds in the kilohertz range for a microprocessor were considered high performance. Recently, standard microprocessors as used in consumer computers have reached speeds in excess of 3-400 megahertz. The processing speed of supercomputers has increased even more dramatically.
Supercomputers today often process data with clock cycles in the gigahertz and terahertz range. Unfortunately, access to memory has not increased in speed as quickly as microprocessor speeds. When a microprocessor desires to perform a memory operation, it takes a large number of clock cycles, often in excess of 100, before the memory operation can be completed. There are some systems in which the microprocessor waits until completion of the memory operation before performing subsequent operations. This, however, is not efficient use of microprocessor cycle time, which has the capability to perform many operations more quickly than a memory operation.
SUMMARY OF THE INVENTION
According to principles of the present invention, a memory unit is provided for tracking memory operation requests from a microprocessor. The memory unit stores an identification of the source of the memory request as well as the type of memory operation being requested. A tag provides the information identifying the source of the memory request. The tag, along with other information is stored in the slot control register for identifying the source of the memory request and tracking the fulfilling of the request and returning the results to the microprocessor.
The slot number is used to index slot control register and a memory request storage which contains a duplicate copy of the memory request. The slot state, also indexed by slot number, contains an identification of the status of the request. The slot state tracks the status of the request; whether it is outstanding, whether to perform a retry in the future, whether the slot is available for use by a new memory operator, or other types of information associated with the pending request. When the reply to an outstanding request is a busy, the slot state is updated and will perform a retry on future clock cycles. A retry is performed along with performing newly received memory requests. As soon as an outstanding request is filled, whether from a newly received request, or a retry of a request, results are provided back to the microprocessor and the slot state is changed to empty indicating it is ready for future memory requests.
A significant advantage of the present invention is that the memory unit is able to perform its function of memory operations and retrieval while letting the central microprocessor perform its job of instruction execution simultaneously. The memory unit runs requests under its own control and provides the requested memory results to the central processor within acceptable time limits for the microprocessor so that the microprocessor can perform other tasks without having to use clock cycles to repeat memory requests. The memory unit reply cycle is not synchronized with the CPU request cycle so that each can operate independently in performing the allocated tasks. This significantly increases the speed at which the overall system can operate both in executing logic and control operations, memory operations and most importantly, increases the speed at which operations requiring memory and arithmetic interaction can occur.
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Alverson Robert L.
Kopser Andrew S.
Carlson David V.
Cray Inc.
Seed IP Law Group PLLC
Song Jasmine
Yoo Do Hyun
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