Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-09-23
2002-07-16
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S110000, C438S014000, C438S016000
Reexamination Certificate
active
06421574
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a methodology for the capture and classification of silicon based defects in the manufacture of semiconductor wafers. More specifically, this invention relates to a methodology for the capture and rapid classification of silicon based defects in the manufacture of semiconductor wafers. Even more specifically, this invention relates to a methodology for the capture and rapid classification of silicon based defects in the manufacture of semiconductor wafers that avoids the inherent lag time between defect capture and engineering disposition of lots on hold from high defectivity.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also know as die) from each wafer is not 100% because of defects that occur to die during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, the cost of defective chips that must be discarded because of a defect or defects must be amortized over the remaining usable chips.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization, ion implantation, thermal annealing, and wet chemical cleaning. These are just a few of the many types of process steps involved in the manufacture of a semiconductor chip. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits. A major part of the analysis process is to determine if defects are caused by one of the process tools, and if so, which tool caused the defects.
As the wafer is placed into different tools during manufacture, each of the tools can produce different types of particles that drop onto the wafer and cause defects that have the potential to “kill” a die that decreases the yield. In order to develop high yield semiconductor processes and to improve existing ones, it is important to identify the sources of the various particles that cause defects and then to prevent the tools from dropping these particles onto the wafer while the wafers are in the tools.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products, a great deal of time, effort and money is being expended by semiconductor manufacturers to capture and classify defects encountered in the manufacture of semiconductor products. Once defects are detected, properly described, and classified, efforts can begin to resolve the cause of the defects and to eliminate the cause of the defects. The biggest problem that faced the semiconductor manufacturers and one of the most difficult to solve was the problem associated with the training and maintenance of a cadre of calibrated human inspectors who can classify all types of defects consistently and without error. This problem was mainly caused by unavoidable human inconsistency and as a solution to this problem; Automatic Defect Classification (ADC) systems were developed.
One such system for automatically classifying defects consists of the following methodological sequence. Obtain a defect image from a review station. View the defect image and assign values to elemental descriptor terms called predicates that are general descriptors such as roundness, brightness, color, hue, graininess, etc. Assign a classification code to the defect based upon the values of all the predicates. A typical ADC system could have 40 or more quantifiable qualities and properties that can be predicates. Each predicate can have a specified range of values and a typical predicate can have a value assigned to it between 1 and 256. The range of values that can be assigned to a predicate is arbitrary and can be any range of values. In this example, a value of 1 could indicate that none of the value is present and a value of 256 would indicate that the quality represented by the predicate is ideal. For example, a straight line would have a value of 1 for predicate indicating roundness, whereas a perfect circle would have a value of 256 for the same predicate. The classification code for each defect is determined by the system from the combination of all the predicate values assigned to the defect. The goal of the ADC system is to be able to uniquely describe all the defect types, in such a manner that a single classification code can be assigned to a defect that has been differentiated from all other types of defects. This is accomplished by a system administrator who trains an artificial intelligence system to recognize various combinations and permutations of the 40 or more predicates to assign the same classification code to the same type of defect. This would result in a highly significant statistical confidence in the probability that the defect, and all other defects of the same type or class, will always be assigned the same classification code by the ADC system. Performing a “best-fit” calculation against all assigned classification codes does this. If the fit is not good enough, the system will assign an “unknown” code, which means the system needs further training for that device/layer/defect.
In order to make the data generated from the ADC system statistically sound, randomness must be maintained in the selection of defects for automatic defect classification process. To accomplish this task, a system has been developed that pre-selects defects for classification based on data from the current scan and previous scans. All previously caught defects and “cluster” defects are removed from the target population and “n” defects are randomly selected from that group. These defect locations are then sent to the review tool for automatic defect classification.
One of the problems with this methodology is the inherent lag time between defect capture and engineering disposition of lots on hold from high defectivity. This disposition often involves scanning more wafers to determine the extent of the defectivity. With the large overhead of recipe download, wafer alignment, and machine queue time, cycle time is severely affected.
FIG. 1
is a flow diagram describing the movement of a selected wafer or wafers through all the processes in a current methodology of manufacturing semiconductor wafers. As is known in the semiconductor manufacturing art, a production lot of wafers can be any selected number of wafers. As is also known in the semiconductor manufacturing art, it is not practical to scan each wafer for defects because inspecting each wafer is extremely time consuming, manpower intensive and equipment intensive. Therefore, a small number of wafers are selected from each production lot to be representative of that production lot. In some cases, only one wafer from a production lot is selected to be tested. This wafer is scanned for defects after each manufacturing process that has been designated to be a process that will be tested. It is also noted that the wafer is not scanne
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Frank Elliot
Nelson H. Donald
Picard Leo
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