Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-06
2002-04-23
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
43, 43, 43, C257S751000, C257S753000
Reexamination Certificate
active
06376356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The invention relates generally to a method of manufacturing a metal wiring in a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal wiring in a semiconductor device capable of solving the problem of poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a semiconductor device.
2. Description of the Prior Art:
A method of manufacturing a conventional metal wiring in a semiconductor device will be explained below by reference to
FIGS. 1A
to
1
C.
Referring now to
FIG. 1A
, a first insulating film
12
is formed on a semiconductor substrate
11
in which a given structure is formed. Then, after a given region of the first insulating film
12
is etched, a metal layer is formed on the etched region of the first insulating film
12
and is then patterned, thus forming an underlying metal wiring
13
. After a second insulating film
14
is formed on the entire structure, a given region of the second insulating film
14
is etched to form a via hole through which the underlying metal wiring
13
is exposed.
At this time, as the semiconductor device is higher integrated, an alignment problem of the underlying wiring and the upper wiring is inevitably generated during the lithography process of forming a via hole. Therefore, in order to reduce the operating speed of the device, the contact area between the via hole and the wiring must be reduced and the contact resistance must be increased. Also, as the second insulating film
14
is etched to form the via hole, if any of the second insulating film
14
is remained within the via hole, the via hole will not be electrically connected to the underlying wiring. In order to prevent this, the second insulating film
14
is over-etched, thus damaging the underlying wiring A.
Referring now to
FIG. 1B
, a diffusion barrier layer
15
and a seed layer
16
are sequentially formed on the entire structure including the via hole. Then, a metal layer
17
(e.g.,a copper layer) is formed on the entire structure by electroplating method, so that the via hose can be buried. At this time, as the diffusion barrier layer
15
and the seed layer
16
are formed in the via hole in a wiring structure of an ultra-fin structure, space into which a metal layer is buried within the via hole is very reduced. Therefore, in the process of forming the seed layer
16
or of forming the metal layer
17
, burial of the via hole is made impossible to cause a void B, thus lowering reliability of the device.
FIG. 1C
is a cross-sectional view of the device in which an upper metal wiring is formed by exposing the second insulating film
14
by CMP process. The upper wiring is disconnected from the underlying wiring by the void B due to poor burial into the via hole having a large step coverage.
The problem in the above process is still severe in case of damascene process used to form a copper wiring. Therefore, there is a need for a technology capable of solving the problem.
SUMMARY OF THE DISCLOSURE
A method of manufacturing a metal wiring in a semiconductor device is disclosed which is capable of solving the problem of poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a semiconductor device.
One disclose method of manufacturing a metal wiring in a semiconductor device comprises the steps of forming a photosensitive film on a semiconductor substrate in which a given structure including an underlying metal wiring is formed, and pattering the photosensitive film to expose the underlying metal wiring; performing a chemical enhancer process by which an chemical enhancer is adhered only to an exposed portion of the underlying metal wiring; depositing a metal layer by CECVD method, wherein the metal layer is selectively deposited at the portion in which the chemical enhancer is formed and the chemical enhancer is floated upwardly as the metal layer is deposited; removing the photosensitive film and the chemical enhancer and then forming a diffusion barrier layer spacer at the sidewall of said metal layer; and forming an insulating film on the entire structure to bury between-the metal layer.
REFERENCES:
patent: 6309957 (2001-10-01), Tu et al.
patent: 6309977 (2001-10-01), Ting et al.
Hyundai Electronics Industries Co.
Marshall Gerstein & Borun
Tsai Jey
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