ROM memory cell not decodable by visual inspection

Details ROM memory cell not decodable by visual inspection ROM memory cell not decodable by visual inspection

2001-06-05

2002-07-16

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257S392000

Reexamination Certificate

active

06420765

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a ROM memory cell not decodable by visual inspection.
BACKGROUND OF THE INVENTION
As is known, ROM memory cells not decodable by visual inspection are used inside smart devices, such as smart cards, to store confidential data (for example personal identification codes to be used in bank transactions or with SIM cards).
ROM memory cells not decodable by visual inspection are also used to store suitable algorithms which can encrypt confidential data.
In both cases, to make the data contained in the ROM memory cells difficult to interpret externally, it is necessary to provide the cells with a protective screen, made from a dedicated metallization layer covering all of the ROM memory cells and not having any other function.
In general, in CMOS integration processes, the ROM memory cells are represented by NMOS transistors having two different values of the threshold voltage V
th
(for example V
th
=0.7 V and V
th
=5.0 V).
Reading of the ROM memory cell content is carried out by feeding the NMOS transistors with a drain-source voltage V
DS
of approximately 1.0 V and a gatesource voltage V
GS
comprised between the two aforementioned threshold voltage values (for example the gate-source voltage V
GS
can have a value of approximately 2.5 V). The obtained drain-source current I
DS
is then compared with a reference current I
REF
which, for example, can have a value corresponding to the half-sum of the drain-source currents of an NMOS transistor with a high threshold (V
th
=5.0 V), and of a NMOS transistor with a low threshold (V
th
=0.7 V).
With reference to
FIG. 1
showing the characteristic which associates the gate-source voltage V
GS
with the drain-source current I
DS
of an NMOS transistor, if the drain-source current I
DS
is greater than the reference current I
REF
(curve “R”), the NMOS transistor is at a logic state “1”, corresponding to the switched on condition. On the other hand, if the drain-source current I
DS
is lower than the reference current I
REF
, the NMOS transistor is at a logic state “0” corresponding to the switched off condition.
It is known that the ROM memory cells incorporated in the smart devices cannot be of the flash EEPROM or EPROM type since both can have problems of retention of the charge stored, which, over a period of time, can lead to loss of the data stored. It is therefore necessary to use alternative approaches. For this purpose, the NMOS transistor representing the logic state “1” (low-threshold transistor) is generally carried out such that it is altogether similar to standard NMOS transistors present in the smart device, whereas the NMOSFET transistor representing the logic state “0” (high-threshold transistor) is carried out using two alternative approaches.
For this purpose,
FIG. 2
shows a transverse cross-section of a first embodiment of a ROM memory cell
1
incorporated in a smart device
50
and comprising a semiconductor material substrate
2
with P
−
-type conductivity.
The ROM memory cell
1
includes a first low-threshold transistor
4
and a second high-threshold transistor
7
. The first transistor
4
is formed by a first conductive region
3
, of type N
+
, defining a drain region, and by a first source region
6
a
, of type N
+
, both formed in a first portion
5
of the substrate
2
. The second transistor
7
is formed by a second source region
6
b
, of type N
+
, providing in a second portion
8
of the substrate
2
adjacent to the first portion
5
and joined to the first source region
6
a
such as to form a second conductive region
6
, and by a third conductive region
9
, of type N
+
, defining a drain region of the second transistor
7
.
The ROM memory cell
1
additionally comprises first and second extension regions
10
,
11
, of type N, operating respectively as a drain extension region and a source extension region of the first transistor
4
, and third and fourth extension regions
12
,
13
of type N operating respectively as a source extension region and a drain extension region of the second transistor
7
.
The first and second extension regions
10
,
11
extend laterally and in a position adjacent respectively to the first and second conductive regions
3
,
6
, and face one another. The first and second extension regions
10
,
11
, delimit a portion of substrate
2
forming a first channel region
15
. Similarly, the third and fourth extension regions
12
,
13
extend laterally and in a position adjacent respectively to the second and third conductive regions
6
,
9
, and face one another. The third and fourth extension regions
12
,
13
delimit a portion of substrate
2
forming a second channel region
18
.
The second channel region
18
accommodates an implanted region
19
, which is more doped than the substrate
2
, to increase the threshold voltage of the second transistor
7
.
Above the first channel region
15
, there is formed a first gate region
20
of polycrystalline silicon of the first transistor
4
. Similarly, above the second channel region
18
, there is formed a second gate region
21
of polycrystalline silicon of the second transistor
7
. The first gate region
20
is isolated from the first channel region
15
by means of a first gate oxide layer
24
, whereas the second gate region
21
is isolated from the second channel region
18
by means of a second gate oxide layer
25
. Above the first and second gate regions
20
,
21
, and above the first, second and third conductive regions
3
,
6
,
9
, there are present a first gate contact region
31
, a second gate contact region
32
, a first drain contact region
33
, a common source contact region
34
, and a second drain contact region
35
of a metal silicide, for example titanium. The first gate region
20
and the first gate contact region
31
are laterally adjoined by first oxide spacers
40
. Similarly, the second gate region
21
and the second gate contact region
32
are laterally adjoined by second oxide spacers
41
.
This first embodiment of the ROM memory cell
1
has the disadvantage that it is relatively costly to carry out, since it is necessary to add to the process phases commonly used additional phases of photolithography and implantation for defining the implanted region
19
.
FIG. 3
shows a cross-section of a second embodiment of the ROM memory cell
1
, in which parts corresponding to the first embodiment in
FIG. 2
have been provided with the same reference numbers. In the second embodiment, the formation of the implanted region
19
and of the third and fourth extension regions
12
,
13
is not provided.
In particular, the lack of definition of the third and fourth extension regions
12
,
13
means that the second gate region
21
is not fully superimposed on the second channel region
18
, which also extends partially below the second oxide spacers
41
. In these design conditions, the application of a gate-source voltage V
GS
to the second transistor
7
is not sufficient to take the latter into a condition of conduction, i.e., to form a continuous reversal region between the second source region
6
b
and its drain region
9
. This is owing to the fact that the portions of the second channel region
18
which are below the second spacers
41
cannot reverse their conductivity (from N to P), in the short period of time in which ROM memory cell
1
reading takes place.
Although this second embodiment of the ROM memory cell
1
has reduced manufacturing costs, since it does not require the operations of photolithography and implantation dedicated to the formation of the implanted region
19
, it nevertheless has the disadvantage that it is difficult to control, since its satisfactory functioning depends on the dimensions of the oxide spacers
41
.
SUMMARY OF THE INVENTION
The technical problem of the present invention is to provide a ROM memory cell not decodable by visual inspection.
According to one embodiment of the invention, the ROM memory cell comprises a substrate of semiconduct

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