Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-07-31
2002-05-07
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S255000, C438S260000, C438S398000, C438S655000, C438S656000, C438S665000, C438S683000, C438S964000
Reexamination Certificate
active
06383905
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method for forming silicide on a polysilicon line of a semiconductor device. More particularly, this invention relates to a method for forming silicide over a controllable micro-rough surface of a polysilicon line, and a device made by the same.
BACKGROUND OF THE INVENTION
Polysilicon has become the prevalent gate material of MOS devices for over a decade. In addition to MOS gates, uses of polysilicon in MOS or other semiconductor devices have also increased prominently. However, although polysilicon provides many advantages, such as self-alignment, over metal as the gate material, its resistance level is still too high to provide interconnections among semiconductor devices. Therefore, after the formation and patterning of a polysilicon layer to form polysilicon lines, a device will typically go through, inter alia, a silicide process for forming a lower resistance silicide layer. As the size of semiconductor devices becomes smaller and smaller, how to provide good quality interconnections for devices having sub-quarter &mgr;m width of polysilicon lines becomes one of the major challenge to the current semiconductor industry.
Although polysilicon has a low contact resistance with silicon, it still exhibits too high a resistance to the interconnection metal materials. Creating a multi-metal stack of the polysilicon (called polycide) having a silicide, e.g., the titanium silicide (TiSi
2
), film is one solution. The silicide film makes a low contact resistance with polysilicon and reduces the overall sheet resistance of the polycide structure. While other silicide materials have been used for reducing contact resistance with polysilicon, a titanium silicide film is the most popular one used in the semiconductor industry.
Growing the titanium silicide film on the polysilicon lines and on active regions of the substrate typically includes two phases. In a first phase, generally called the C49 phase formation, the titanium is first deposited on the surface of the device. The deposition of titanium (Ti) is then followed by a first rapid thermal anneal (RTA) step to cause the titanium reacted with the underlying silicon substrate or polysilicon lines and thus form the titanium silicide film. Once the titanium silicide film has been formed, those unreacted portions of the titanium are then removed, forming self-aligned silicide (Salicide) on polysilicon and active regions only.
In a second phase, the previously formed titanium silicide film will go through another anneal step, such as a second RTA step, to further reduce the overall sheet resistance of the newly formed titanium silicide. This second phase of transformation is commonly referred to a C54 phase. A simplified structure of a device produced after the C54 phase is illustrated in FIG.
1
. The current silicide technology, however, faces two major difficulties for future sub-quarter &mgr;m technology of silicide over polysilicon lines. First, as the width of the polysilicon lines is reduced to being in the sub-quarter &mgr;m range, it is more difficult to grow a smaller grain size titanium silicide during the C49 phase. Second, for smaller width of the polysilicon lines higher annealing temperature is required for the C54 phase transformation without resulting in TiSi
2
agglomeration.
Furthermore, when the width of the polysilicon lines are reduced to about 0.1 &mgr;m the formation of titanium silicide having the grain size larger than 0.1 &mgr;m during the C49 phase will suppress the grain growth of the titanium silicide during the later C54 phase. As a result, the titanium silicide will have an undesirable higher sheet resistance. To cure this problem, a much higher RTA temperature for the titanium silicide is required. The much higher RTA temperature is very undesirable because it will not only increase difficulties in manufacture, e.g., higher costs or equipment problems, but also may cause device failure due to the thermal budget limitation of the device during manufacturing, and the introduced defects such as the TiSi
2
agglomeration.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method for manufacturing a semiconductor device having low sheet resistance suicide over polysilicon lines of sub-quarter &mgr;m or even less than 0.1 &mgr;m width. In one embodiment of the invention, small indentations or scratches are formed on the surface of the polysilicon lines before the formation of the silicide.
The features and advantages of the present invention will be made apparent, by way of illustration and not by limitation, in the following description of embodiments illustrated in the annexed drawings. The figures show enlarged portions of certain areas to better illustrate the inventive feature and none of the figures are understood as being in scale or exact proportion.
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Carlson David V.
Jorgenson Lisa K.
Lytle Craig P.
Smith Matthew
STMicroelectronics Inc.
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