Silicon wafers for CMOS and other integrated circuits

Details Silicon wafers for CMOS and other integrated circuits Silicon wafers for CMOS and other integrated circuits

1999-09-22

2002-07-23

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Subsequent separation into plural bodies

C438S231000, C148SDIG004

Reexamination Certificate

active

06423615

ABSTRACT:

BACKGROUND
The present invention relates generally to silicon wafers for complementary metal-oxide-semiconductor (CMOS) and other integrated circuits.
As integrated semiconductor devices continue to grow in complexity, there is a continuing need to increase the density of the semiconductor devices. However, the increase in density can cause various problems some of which can lead to device failure. One such problem is “latch-up”, which can be caused by the close proximity of n-channel and p-channel transistors in CMOS integrated circuits. For example, a typical CMOS integrated circuit fabricated on a p-type substrate has a p-channel transistor fabricated in an n-well and an n-channel transistor fabricated in a p-well with only a short distance separating the wells. Such a structure inherently forms a parasitic lateral bipolar n-p-n structure and a parasitic vertical p-n-p bipolar structure. Under certain biasing conditions, the p-n-p structure can supply base current to the n-p-n structure, or vice-versa, causing a current to flow from one well to the other well. The large current can damage the integrated circuit.
One technique for reducing the incidence of latch-up is to fabricate the CMOS transistors on an epitaxial silicon wafer
10
that includes, for example, a lightly boron-doped epitaxial layer
12
deposited on a heavily boron-doped substrate
14
(FIG.
1
A). Electrical circuit elements
16
,
18
are fabricated in the top epitaxial layer
12
as shown, for example, in FIG.
1
B. The heavily doped substrate
14
helps prevent device failure that can result from latch-up and functions as a region into which metallic impurities are trapped.
Unfortunately, these epitaxial silicon wafers can be relatively expensive. A substantial portion of the cost of manufacturing such wafers is a result of formation of the lightly-doped epitaxial layer. Increased manufacturing costs also can result from the high cost of equipment used to fabricate the epitaxial layer, the relatively low throughput associated with the formation of the epitaxial layer, and the complexity of quality control. Accordingly, it would be advantageous to reduce the manufacturing costs associated with boron-doped silicon wafers without adversely impacting circuit performance.
SUMMARY
In general, techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Various features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.


REFERENCES:
patent: 5183777 (1993-02-01), Doki et al.
patent: 5770504 (1998-06-01), Brown et al.
patent: 5897705 (1999-04-01), Siebert et al.
Stanley Wolf Silicon Processing for the VSLI Era vol! Lattice Press 1986 pp. xxiii, 8-9, 12-14,23-25,27.*
Suzuki et al., “Boron Out Diffusion From Si Substrates In Various Ambients”, Sold-State Electronics, vol. 41, No. 8, Aug. 1997, pp. 1095-1097.
Matsushita, Y., “Hydrogen Annealed Silicon Wafer: Hi Wafer”, Silicon Wafer Symposium, SEMI 1998, R1-R3.

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