Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-07-24
2002-07-09
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S200000
Reexamination Certificate
active
06418520
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-209775 filed on Jul. 23, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address converting circuit configured to convert a virtual address inputted from outside into a physical address. Especially, the present invention is intended for a circuit included in a microprocessor.
2. Related Background Art
Recently, processors generally employ a virtual addressing method which allocates a part of a virtual address space to a main memory. By employing the virtual addressing method, application program can perform memory-access with disregard to the main memory, thereby simplifying programming.
The virtual address is obtained by adding a base address and an offset address. Inside of the processor is provided with an address converting circuit, i.e. TLB:Translation Lookaside Buffer for converting the virtual address into the physical address.
FIG. 1
is a block diagram showing schematic configuration of a conventional address converting circuit. The address converting circuit of
FIG. 1
has an adder
121
for adding the base address [31:0] and the offset address [31:0], a CAM (Contents Addressable Memory) for comparing the virtual address outputted from the adder
121
with the virtual address corresponding to data stored to the cache memory, a physical address storing section
123
for storing the physical address corresponding to data stored to the cache memory, and a selector
124
for reading out the physical address [31:20] corresponding to the virtual address that access is required from the physical address storing section
123
.
Because the circuit of
FIG. 1
performs a comparison by the CAM
122
after the virtual address expressing an added result is outputted from the adder
121
, a processing time of all the TLBs is decided by the calculating time of the adder
121
. Because of this, it is impossible to process at high speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an address converting circuit that it is possible to convert a virtual address that access is required into a physical address at high speed.
In order to achieve the foregoing object, an address conversion circuit for converting a virtual address that access is required into a physical address, comprising:
upper bit string storing means configured to store an upper bit string of the virtual address corresponding to data stored to a cache memory;
an upper bit string adder configured to add both of the upper bit strings of a base address and an offset address of the virtual address, by predicting in advance with or without carry when both of a lower bit strings of the base address and the offset address of the virtual address that access is required are added;
a carry calculator configured to calculate carry information when both of the lower bit strings of the base address and the offset address of the virtual address that access is required are added;
an upper bit string comparator configured to compare a result added by the upper bit string adder with the upper bit string of the virtual address stored to the upper bit string storing means, and
an address converter configured to convert the virtual address that access is required into the physical address, based on a result calculated by the carry calculator and a result compared by the upper bit stream comparator.
Furthermore, an address converter configured to convert a virtual address that access is required into a physical address, comprising:
upper bit string storing means configured to store an upper bit string of the virtual address corresponding to data stored to a cache memory;
carry information storing means configured to calculate carry information in case of adding both of a lower bit strings of a base address and an offset address of the virtual address corresponding to data stored to the cache memory;
a carry information calculator configured to calculate the carry information in case of adding both of the lower bit strings of the base address and the offset address of the virtual address that access is required;
an upper bit string comparator configured to compare the upper bit strings of the base address and the offset address of the virtual address that access is required with the upper bit strings of the base address and the offset address of the virtual address stored to the upper bit string storing means, and
address converter for converting the virtual address that access is required into the physical address based on information stored to the carry information storing means, carry information calculated by the carry information, and the result compared by the upper bit string comparator.
Furthermore, an address converting circuit configured to convert a virtual address that access is required into a physical address, comprising:
upper bit string storing means configured to store an upper bit string of the virtual address corresponding to data stored to a cache memory;
an intermediate bit string storing means configured to store intermediate bit strings of the virtual address corresponding to data stored to the cache memory;
an intermediate bit string adder configured to add both of intermediate bit strings of a base address and an offset address of the virtual address, by predicting in advance with or without a carry in case of adding both lower bit strings of the base address and the offset address of the virtual address that access is required;
an intermediate bit string comparator configured to compare the result added by the intermediate bit string adder with the intermediate bit string of the virtual address stored to the intermediate bit string storing means;
an upper bit string comparator configured to compare the upper bit string of the base address and the offset address of the virtual address that access is required with the upper bit strings of the base address and the offset address of the virtual address stored to the upper bit stream storing means;
carry information calculator configured to calculate the carry information in case of adding both of the lower bit strings of the base address and the offset address of the virtual address that access is required, and
an address converter configured to convert the virtual address that access is required into the physical address based on the result compared by the upper bit stream comparator, the result compared by the intermediate bit stream comparator, and the result calculated by the carry information calculator.
According to the present invention, it is possible to perform comparing process of a virtual address and to convert the virtual address into the physical address before the carry information is calculated, because the comparing process of the upper bit string and the intermediate bit string are performed in parallel with calculation of the carry information from the lower bit string of the virtual address.
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Hayakawa Shigeyuki
Midorikawa Tsuyoshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Thai Tuan V.
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