Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-07
2002-09-03
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S093000, C257S329000, C257S330000, C257S374000, C257S393000, C257S446000, C257S499000, C257S501000, C257S506000, C257S510000, C257S513000, C257S519000, C257S520000
Reexamination Certificate
active
06445048
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of semiconductors.
One of the common problems encountered in the fabrication of semiconductor components is effective isolation of doped regions in the semiconductor substrate. The problem area arises, in particular, when a semiconductor component contains doped regions that are indiffused relatively far. Examples thereof are CMOS wells in integrated circuits or annular doping regions that surround the cell array in power transistors or IGBTs and are intended to dissipate the current flowing in the edge area. In many cases, these regions are intended to be spatially and electrically isolated from other doping regions.
One possibility for electrically and spatially isolating doped regions would be to implant them with such a large spacing that they do not diffuse into one another in the course of the subsequent diffusion processes, but rather maintain a sufficiently large spacing. In such a case, the spacing of the implantations must be larger than the spacing desired at the end of the fabrication process by a sum of the extents of the outdiffusion from the doping regions. Therefore, undesirably large structures are produced for deep diffusion regions.
U.S. Pat. No. 5,525,821 to Harada et al. describes a method in which diffusion regions are produced first. These diffusion regions are subsequently isolated from one another by deep trench structures. Although the method makes it possible to fabricate structures with a small lateral extent, there is nonetheless, a disadvantage that the depth of the trenches must reach at least the depth of the diffusion regions. Consequently, more complicated patterning steps are required. There are also more limitations if the intention is to provide for the fabrication of additional trenches, which are intended to be utilized for trench transistors, for example, at the same time as the trenches, for isolating the diffusion regions. Because the diffusion regions already predetermine the depth of the trenches, adequate patterning freedoms no longer remain for optimizing the trench transistors.
Moreover, isolating diffusion regions by trenches that are allowed to have a smaller depth than the diffusion regions is disclosed in U.S. Pat. No. 5,430,324 to Bencuya or in British Patent No. GB 2,314,206. However, there are two problem areas associated with these references. First of all, doping regions have to be implanted with a sufficiently large spacing. On the other hand, there is a risk that the small depth of the trenches does not ensure sufficient spatial and electrical isolation of the doped regions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor configuration having trenches for isolating doped regions that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a possibility for effectively isolating doped regions by trenches in a semiconductor substrate and allows the smallest possible structure sizes and the greatest possible freedoms in the configuration of the trenches.
With the foregoing and other objects in view, there, is provided, in accordance with the invention, a semiconductor configuration, including a substrate having a first conduction type, an edge, and a surface, a transistor configuration disposed at the substrate, the transistor configuration formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode, at least two regions having a second conduction type and disposed between the transistor configuration and the substrate edge, the at least two regions extending from the surface of the substrate into the substrate and surrounding the transistor configuration, and at least two adjacent insulating trench regions disposed between the at least two regions and extending from the surface of the substrate into the substrate, the at least two regions isolated from one another by the at least two adjacent insulating trench regions.
As already described, the necessity of isolating doped regions in different areas of a semiconductor configuration may arise. Thus, it may be necessary to isolate doped regions, for example, in the active area of a semiconductor configuration, i.e., in that area in which the transistors are disposed. Likewise, the case may arise where doped regions in the area of the edge structures of the semiconductor configuration, i.e., between the transistor configuration and the substrate edge, have to be isolated from one another. In such an area, for example, it is possible to provide doped regions between the transistor configuration and the substrate edge, which extend from the surface of the substrate into the substrate and surround the transistor configuration as a ring. The transistor configuration, itself, may be made from any desired number and type of transistors. In particular, transistors that are configured as field-effect transistors and have at least two doped regions embedded in the substrate. Also, at least one gate electrode can be used. In principle, however, it is also possible to provide bipolar transistors, for example.
For effective isolation of the doped regions, at least two adjacent, insulating trench regions are now respectively provided that are disposed between the doped regions and extend from the surface of the substrate into the substrate. Consequently, according to the invention, not just one individual trench is situated between two doped regions—such a trench being inadequate, under certain circumstances, for effective isolation. Rather, two or more trenches are disposed between the doped regions. Thus, even with trenches having a relatively small depth that is smaller than the depth of the doped regions, very good electrical and spatial isolation of the doped regions can still be obtained. The depth of the trenches can be adapted to the conditions for producing trench transistors, for example.
As described, the present invention affords relatively great freedoms in the configuration of the depth of the trenches for isolating the doped regions. Thus, these trenches may have a depth that is smaller than the depth of the doped regions. Of course, it is also possible to provide trenches whose depth corresponds to the depth of the doped regions, or whose depth is greater than the depth of the doped regions.
The trenches can be filled with different materials. Thus, for example, each trench region or at least a portion of the trench regions can be filled with an insulation layer or can be formed by an insulation layer. As an alternative, however, a conductive layer surrounded by an insulation layer can be present in the trench region. All that has to be ensured is that sufficient insulation of the doped regions relative to one another can be attained. Consequently, different materials that can be adapted to the respective conditions can also be chosen for the insulation layer or the conductive layer in the trench region. An oxide layer or a nitride layer, for example, may be provided as the insulation layer, and a polysilicon layer, for example, may be provided as the conductive layer.
In accordance with another feature of the invention, each of the trench regions is formed by a conductive layer surrounded by an insulation layer.
If trench regions being made from a conductive layer are provided, then it is possible to provide conductive interconnection between the individual trench regions. Such a configuration achieves an ability to hold the interconnected trench regions at a uniform potential. In this case, in order to obtain an exactly defined potential, individual trenches or all of the trenches that have a conductive layer can be connected to one of the electrodes of the transistor configuration, for example, to a gate electrode or a cathode electrode. Thus, for example, at least the innermost trench regions, which are disposed nearest to the transistor configuration, can be conductively connected
Flynn Nathan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Sefer Ahmed N.
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